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-rw-r--r--.gitmodules3
-rw-r--r--Makefile73
-rw-r--r--README.md2
-rw-r--r--bitfile/README.md7
-rw-r--r--bootrom/bram.mk79
-rw-r--r--bootrom/common/bram.ld40
-rw-r--r--bootrom/common/mem.awk63
-rw-r--r--bootrom/demo/Makefile5
-rw-r--r--bootrom/demo/demo.S71
-rw-r--r--bootrom/demo/hello_msg.txt37
-rw-r--r--bsp/env/common.mk44
-rw-r--r--bsp/env/encoding.h1313
-rw-r--r--bsp/env/freedom-e300-arty/entry.S81
-rw-r--r--bsp/env/freedom-e300-arty/init.c61
-rw-r--r--bsp/env/freedom-e300-arty/link.lds163
-rw-r--r--bsp/env/freedom-e300-arty/openocd.cfg16
-rw-r--r--bsp/env/freedom-e300-arty/platform.h119
-rw-r--r--bsp/env/freedom-e300-hifive1/entry.S81
-rw-r--r--bsp/env/freedom-e300-hifive1/init.c187
-rw-r--r--bsp/env/freedom-e300-hifive1/link.lds163
-rw-r--r--bsp/env/freedom-e300-hifive1/openocd.cfg21
-rw-r--r--bsp/env/freedom-e300-hifive1/platform.h129
-rw-r--r--bsp/env/hifive1.h81
-rw-r--r--bsp/env/syscall.c (renamed from software/shared/syscall.c)80
-rw-r--r--bsp/include/sifive/bits.h35
-rw-r--r--bsp/include/sifive/const.h17
-rw-r--r--bsp/include/sifive/devices/aon.h88
-rw-r--r--bsp/include/sifive/devices/clint.h14
-rw-r--r--bsp/include/sifive/devices/gpio.h24
-rw-r--r--bsp/include/sifive/devices/otp.h23
-rw-r--r--bsp/include/sifive/devices/plic.h31
-rw-r--r--bsp/include/sifive/devices/prci.h56
-rw-r--r--bsp/include/sifive/devices/pwm.h37
-rw-r--r--bsp/include/sifive/devices/spi.h80
-rw-r--r--bsp/include/sifive/devices/uart.h27
-rw-r--r--bsp/include/sifive/sections.h16
-rwxr-xr-xbsp/tools/openocd_upload.sh5
m---------openocd0
m---------riscv-gnu-toolchain0
m---------riscv-tests0
-rw-r--r--software/demo_gpio/Makefile14
-rw-r--r--software/demo_gpio/demo_gpio.c115
-rw-r--r--software/demo_gpio/plic_driver.c (renamed from software/shared/drivers_sifive/plic.c)18
-rw-r--r--software/dhrystone/Makefile20
-rw-r--r--software/dhrystone/dhry.h423
-rw-r--r--software/dhrystone/dhry_1.c385
-rw-r--r--software/dhrystone/dhry_2.c192
-rw-r--r--software/dhrystone/dhry_printf.c271
-rw-r--r--software/dhrystone/dhry_stubs.c31
-rw-r--r--software/hello/Makefile6
-rw-r--r--software/hello/hello.c8
-rw-r--r--software/shared/Makefile.shared48
-rw-r--r--software/shared/drivers_sifive/plic.h70
l---------software/shared/entry.S1
-rw-r--r--software/shared/gpio.h10
-rw-r--r--software/shared/init.c48
-rw-r--r--software/shared/shared.h73
-rw-r--r--software/shared/spi.h8
-rw-r--r--software/shared/uart.h12
59 files changed, 4391 insertions, 734 deletions
diff --git a/.gitmodules b/.gitmodules
index 9cadd28..5be7ee5 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,6 +4,3 @@
[submodule "riscv-gnu-toolchain"]
path = riscv-gnu-toolchain
url = http://github.com/riscv/riscv-gnu-toolchain.git
-[submodule "riscv-tests"]
- path = riscv-tests
- url = http://github.com/riscv/riscv-tests.git
diff --git a/Makefile b/Makefile
index a9f9122..41d01c0 100644
--- a/Makefile
+++ b/Makefile
@@ -17,23 +17,22 @@ help :
@echo " tools:"
@echo " Install compilation & debugging tools"
@echo ""
- @echo " software [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
+ @echo " software [PROGRAM=demo_gpio BOARD=freedom-e300-arty]:"
@echo " Build a software program to load with the"
@echo " debugger."
@echo ""
- @echo " run_debug [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
+ @echo " run_debug [PROGRAM=demo_gpio BOARD=freedom-e300-arty]:"
@echo " Launch OpenOCD & GDB to load or debug "
@echo " running programs."
+ @echo ""
+ @echo " upload [PROGRAM=demo_gpio BOARD=freedom-e300-arty]:"
+ @echo " Launch OpenOCD to flash your program to the"
+ @echo " on-board Flash"
@echo ""
- @echo " run_openocd [PLATFORM=freedom-e300]:"
- @echo " run_gdb [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
- @echo " Launch OpenOCD & GDB seperately"
- @echo ""
- @echo " fpga [BOOTROM=demo]:"
- @echo " Rebuild the image (including Boot SW) to"
- @echo " reprogram the FPGA image for Arty Board. "
- @echo ""
-
+ @echo " run_openocd [BOARD=freedom-e300-arty]:"
+ @echo " run_gdb [PROGRAM=demo_gpio BOARD=freedom-e300-arty]:"
+ @echo " Launch OpenOCD or GDB seperately"
+ @echo ""
@echo " For more information, visit dev.sifive.com"
@@ -43,14 +42,12 @@ help :
toolchain_srcdir := $(srcdir)/riscv-gnu-toolchain
toolchain32_wrkdir := $(wrkdir)/riscv32-gnu-toolchain
-toolchain64_wrkdir := $(wrkdir)/riscv64-gnu-toolchain
toolchain_dest := $(CURDIR)/toolchain
openocd_srcdir := $(srcdir)/openocd
openocd_wrkdir := $(wrkdir)/openocd
openocd_dest := $(CURDIR)/toolchain
-target64 := riscv64-unknown-linux-gnu
target32 := riscv32-unknown-linux-gnu
@@ -58,18 +55,12 @@ target32 := riscv32-unknown-linux-gnu
all: tools
@echo All done.
-tools: tools64 tools32 openocd
+tools: tools32 openocd
@echo All Tools Installed
-tools64: $(toolchain_dest)/bin/$(target64)-gcc
tools32: $(toolchain_dest)/bin/$(target32)-gcc
openocd: $(openocd_dest)/bin/openocd
-$(toolchain_dest)/bin/$(target64)-gcc: $(toolchain_srcdir)
- mkdir -p $(toolchain64_wrkdir)
- cd $(toolchain64_wrkdir); $(toolchain_srcdir)/configure --prefix=$(toolchain_dest)
- $(MAKE) -C $(toolchain64_wrkdir)
-
$(toolchain_dest)/bin/$(target32)-gcc: $(toolchain_srcdir)
mkdir -p $(toolchain32_wrkdir)
cd $(toolchain32_wrkdir); $(toolchain_srcdir)/configure --prefix=$(toolchain_dest) --with-arch=RV32IMA
@@ -89,27 +80,12 @@ uninstall:
rm -rf -- $(toolchain_dest)
#############################################################
-# This Section is for MCS File Generation (
-#############################################################
-
-BOOTROM ?= demo
-BOOTROM_DIR = $(srcdir)/bootrom/$(BOOTROM)/
-
-.PHONY:
-fpga:
- cd $(BOOTROM_DIR);\
- make mcs
-
-fpga_clean:
- cd $(BOOTROM_DIR);\
- make clean
-
-#############################################################
-# This Section is for Software (non-boot) compilation
+# This Section is for Software Compilation
#############################################################
-
-PROGRAM ?= demo_gpio
+BOARD ?= freedom-e300-arty
+PROGRAM ?= demo_gpio
PROGRAM_DIR = $(srcdir)/software/$(PROGRAM)
+PROGRAM_ELF = $(srcdir)/software/$(PROGRAM)/$(PROGRAM)
.PHONY: software
software:
@@ -120,14 +96,27 @@ software_clean:
cd $(PROGRAM_DIR);\
make clean
+dasm: software
+ cd $(PROGRAM_DIR); \
+ $(toolchain_dest)/bin/riscv32-unknown-elf-objdump -D $(PROGRAM_ELF)
+
+#############################################################
+# This Section is for uploading a program to SPI Flash
+#############################################################
+OPENOCD_UPLOAD = $(srcdir)/bsp/tools/openocd_upload.sh
+OPENOCDCFG ?= $(srcdir)/bsp/env/$(BOARD)/openocd.cfg
+
+upload:
+ $(OPENOCD_UPLOAD) $(PROGRAM_ELF) $(OPENOCDCFG)
+
#############################################################
# This Section is for launching the debugger
#############################################################
+
OPENOCD = $(toolchain_dest)/bin/openocd
-PLATFORM ?= freedom-e300
-OPENOCDARGS += -f $(srcdir)/riscv-tests/debug/targets/$(PLATFORM)/openocd.cfg
+OPENOCDARGS += -f $(OPENOCDCFG)
-GDB = $(toolchain_dest)/bin/riscv64-unknown-elf-gdb
+GDB = $(toolchain_dest)/bin/riscv32-unknown-elf-gdb
GDBCMDS += -ex "target extended-remote localhost:3333"
GDBARGS =
diff --git a/README.md b/README.md
index 307612e..a9105e4 100644
--- a/README.md
+++ b/README.md
@@ -18,7 +18,7 @@ git clone --recursive http://github.com/sifive/freedom-e-sdk.git
Ubuntu packages needed:
- $ sudo apt-get install autoconf automake libmpc-dev libmpfr-dev libgmp-dev gawk bison flex texinfo libtool libusb-1.0-0-dev
+ $ sudo apt-get install autoconf automake libmpc-dev libmpfr-dev libgmp-dev gawk bison flex texinfo libtool libusb-1.0-0-dev make g++ pkg-config
Next, build the tools:
diff --git a/bitfile/README.md b/bitfile/README.md
deleted file mode 100644
index 8dbf9c5..0000000
--- a/bitfile/README.md
+++ /dev/null
@@ -1,7 +0,0 @@
-Download the bitfile and associated files from:
-
-https://dev.sifive.com/develop/freedom-e300-arty-dev-kit/
-
-Place them in the freedom-e-sdk/bitfile/ directory.
-
-
diff --git a/bootrom/bram.mk b/bootrom/bram.mk
deleted file mode 100644
index 2c7875a..0000000
--- a/bootrom/bram.mk
+++ /dev/null
@@ -1,79 +0,0 @@
-ifndef _BRAM_MK
-_BRAM_MK := # defined
-
-BRAM_ADDR := 0x1000
-
-BASEDIR := $(dir $(lastword $(MAKEFILE_LIST)))
-BASEDIR := $(BASEDIR:/=)
-DATADIR := $(BASEDIR)/common
-
-LDSCRIPT := $(DATADIR)/bram.ld
-MEMSCRIPT := $(DATADIR)/mem.awk
-
-BITFILEDIR := $(BASEDIR)/../bitfile
-BITFILE_VERSION ?= 0-1
-
-BITFILE := $(BITFILEDIR)/freedom-e300-arty-$(BITFILE_VERSION).bit
-CFGFILE := $(BITFILEDIR)/FreedomE-$(BITFILE_VERSION).cfg
-MEMINFO := $(BITFILEDIR)/freedom-e300-arty-$(BITFILE_VERSION).mmi
-BRAM_INST := `cat $(BITFILEDIR)/freedom-e300-arty-$(BITFILE_VERSION)-bootrom.txt`
-
-XLEN = 32
-BRAM_WIDTH=64
-
-all: mcs
-
-$(BITFILE):
- @echo "In order to get Version $(BITFILE_VERSION) of the bitfile:"
- @echo ""
- @cat $(BITFILEDIR)/README.md
-
-CC := ../../toolchain/bin/riscv$(XLEN)-unknown-elf-gcc
-UPDATEMEM ?= updatemem
-
-CDEFINES += -DCFG_STRING=\"$(CFGFILE)\"
-
-CFLAGS ?= -m$(XLEN) -O2 -std=c11 -pedantic -Wall \
- -nostartfiles -fno-common -mcmodel=medany -g \
- $(CDEFINES)
-
-LDFLAGS ?= -T$(LDSCRIPT) -static -nostdlib
-OBJCOPY ?= objcopy
-elf: $(PROG).elf
-hex: $(PROG).hex
-mem: $(PROG).impl.mem
-mcs: $(PROG).mcs
-
-$(PROG).elf: $(SRCS) $(EXTRAS) $(CFGFILE)
- $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(SRCS)
-
-$(PROG).hex: $(PROG).elf
- $(OBJCOPY) -S -O verilog --change-addresses -$(BRAM_ADDR) $< $@
-
-# Manually reverse the byte order due to limitations in UpdateMEM.
-# Per UG898: "When UpdateMEM inputs data, it takes data from data input
-# files in Bit Lane sized chunks from the most right value first to the
-# left most. For example, if the first 64 bits of input data are
-# 0xB47DDE02826A8419 then the value 0xB4 is the first value to be set
-# into a Block RAM."
-$(PROG).impl.mem: $(PROG).hex $(MEMSCRIPT)
- awk -v WIDTH=$(BRAM_WIDTH) -v REVERSE=1 -f $(MEMSCRIPT) $< > $@
-
-.PHONY: $(PROG).mcs
-$(PROG).mcs : $(BITFILE) $(PROG).impl.mem
- @echo ""
- @echo ""
- @echo "TO COMPLETE THE BUILD OF $(PROG).mcs, "
- @echo "ENTER THE FOLLOWING IN THE VIVADO TCL WINDOW:"
- @echo ""
- @echo "cd `pwd`"
- @echo ""
- @echo "exec $(UPDATEMEM) -meminfo $(MEMINFO) -data $(PROG).impl.mem -proc $(BRAM_INST) -bit $(BITFILE) --out $(PROG).bit -force"
- @echo ""
- @echo "write_cfgmem -format mcs -interface spix4 -size 16 -loadbit {up 0x0 $(PROG).bit} -file $(PROG).mcs -force"
- @echo ""
-
-clean:
- rm -f -- $(foreach ext,elf hex impl.mem bit mcs,$(PROG).$(ext))
-
-endif # _BRAM_MK
diff --git a/bootrom/common/bram.ld b/bootrom/common/bram.ld
deleted file mode 100644
index 45df67f..0000000
--- a/bootrom/common/bram.ld
+++ /dev/null
@@ -1,40 +0,0 @@
-OUTPUT_ARCH("riscv")
-ENTRY(_start)
-
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00001000, LENGTH = 4K
- ram (rwx) : ORIGIN = 0x80000000, LENGTH = 256M
-}
-
-SECTIONS
-{
- PROVIDE(_rom = ORIGIN(rom));
- PROVIDE(_rom_end = _rom + LENGTH(rom));
- PROVIDE(_ram = ORIGIN(ram));
- PROVIDE(_ram_end = _ram + LENGTH(ram));
-
- .text : {
- PROVIDE(_ftext = .);
- *(.text.init)
- *(.text .text.* .gnu.linkonce.t.*)
- PROVIDE(_etext = .);
- } > rom
-
- .rodata : {
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- } > rom
-
- .bss : ALIGN(8) {
- PROVIDE(_fbss = .);
- *(.bss .bss.* .gnu.linkonce.b.*)
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- . = ALIGN(8);
- PROVIDE(_ebss = .);
- } > ram
-
- . += 0x1000;
- PROVIDE(_sp = NEXT(0x1000));
-
- PROVIDE(_end = .);
-}
diff --git a/bootrom/common/mem.awk b/bootrom/common/mem.awk
deleted file mode 100644
index 3003b56..0000000
--- a/bootrom/common/mem.awk
+++ /dev/null
@@ -1,63 +0,0 @@
-BEGIN {
- RS = ORS = "\r\n"
- addr = 0
- buf = ""
- limit = (WIDTH > 0 ? WIDTH / 4 : 16)
- print "@00000000"
-}
-
-# Portable strtonum() replacement
-function atoi(str, x, n, i, b, c) {
- if (str ~ /^0[0-7]*$/) {
- i = 2
- b = 8
- } else if (str ~ /^0[xX][[:xdigit:]]+$/) {
- i = 3
- b = 16
- } else {
- return str
- }
-
- x = 0
- n = length(str)
- for (; i <= n; i++) {
- c = tolower(substr(str, i , 1))
- c = index("123456789abcdef", c)
- x = (x * b) + c
- }
- return x
-}
-
-function out(x) {
- addr++
- buf = (REVERSE ? buf x : x buf)
- if (length(buf) >= limit) {
- print buf
- buf = ""
- }
-}
-
-function pad(n) {
- while (addr < n) {
- out("00")
- }
-}
-
-match($1, /^@[[:xdigit:]]+/) {
- pad(atoi("0x" substr($1, RSTART+1, RLENGTH-1)))
- next
-}
-
-{
- for (i = 1; i <= NF; i++) {
- out($i)
- }
-}
-
-END {
- align = limit / 2
- pad(int((addr + align - 1) / align) * align)
- if (length(buf) > 0) {
- print buf;
- }
-}
diff --git a/bootrom/demo/Makefile b/bootrom/demo/Makefile
deleted file mode 100644
index dfe3663..0000000
--- a/bootrom/demo/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-PROG := demo
-SRCS := demo.S
-EXTRAS := hello_msg.txt
-
-include ../bram.mk
diff --git a/bootrom/demo/demo.S b/bootrom/demo/demo.S
deleted file mode 100644
index c6f2618..0000000
--- a/bootrom/demo/demo.S
+++ /dev/null
@@ -1,71 +0,0 @@
-#define UART_BASE 0x48000000
-#define SPI_BASE 0x48001000
-#define GPIO_BASE 0x48002000
-
-#ifndef CFG_STRING
-#error Must define CFG_STRING
-#endif
-
- .globl _start
-_start:
- j uart_init
- nop
- nop
- .word cfgstr
-
-uart_init:
- // a1 = UART_TX
- // a2 = hello_msg_end
- // for (a0 = hello_msg_start; a0 != a2; ++ a0){
- // while (a3 = TX_READY == 0);
- // a3 = *a0
- // *a1 = a3
- // }
-
- la a0, hello_msg_start
- la a2, hello_msg_end
- li a1, UART_BASE
-
-uart_loop:
- lw a3, 4(a1) // Wait until non-zero (uart can send data).
- beqz a3, uart_loop
-
- lb a3, 0(a0) // read the next character in hello_msg
- sw a3, 0(a1) // Write the current character.
- addi a0, a0, 1 // increment the pointer.
- bne a0, a2, uart_loop
-
-gpio_init:
- li a0, GPIO_BASE
- li t0, 0xFFFF0000
- sw t0, 4(a0)
-
-gpio_loop:
- // For Red LEDs, increment manually.
- li t0, 0x1
- sw t0, (a0)
- li t0, 0x2
- sw t0, (a0)
- li t0, 0x4
- sw t0, (a0)
- li t0, 0x8
- sw t0, (a0)
-
- // For Blue and Green LEDs, sample the switches & buttons
-
- lw t0, (a0)
- srli t0, t0, 16
- andi t0, t0, 0xFF
- slli t0, t0, 4
- sw t0, (a0)
-
- j gpio_loop
-
- .section .rodata
-
-hello_msg_start:
- .incbin "hello_msg.txt"
-hello_msg_end:
-
-cfgstr:
- .incbin CFG_STRING
diff --git a/bootrom/demo/hello_msg.txt b/bootrom/demo/hello_msg.txt
deleted file mode 100644
index c3cb3f2..0000000
--- a/bootrom/demo/hello_msg.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-
- SIFIVE, INC.
-
- 5555555555555555555555555
- 5555 5555
- 5555 5555
- 5555 5555
- 5555 5555555555555555555555
- 5555 555555555555555555555555
- 5555 5555
- 5555 5555
- 5555 5555
-5555555555555555555555555555 55555
- 55555 555555555 55555
- 55555 55555 55555
- 55555 5 55555
- 55555 55555
- 55555 55555
- 55555 55555
- 55555 55555
- 55555 55555
- 555555555
- 55555
- 5
-
- SiFive RISC-V Coreplex
-
-Welcome to the Arty FPGA Freedom E Dev Kit.
-The red LEDs are blinking very fast and appear
-dim. Try pressing the buttons and switches to control
-the blue and green LEDs. You can try using the
-debugger to step through the boot code.
-
-
-
-
-
diff --git a/bsp/env/common.mk b/bsp/env/common.mk
new file mode 100644
index 0000000..42c0f96
--- /dev/null
+++ b/bsp/env/common.mk
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+BOARD ?= freedom-e300-hifive1
+ENV_DIR = $(BSP_BASE)/env
+PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
+
+ASM_SRCS += $(PLATFORM_DIR)/entry.S
+C_SRCS += $(PLATFORM_DIR)/init.c
+C_SRCS += $(ENV_DIR)/syscall.c
+
+LINKER_SCRIPT := $(PLATFORM_DIR)/link.lds
+
+INCLUDES += -I.
+INCLUDES += -I$(BSP_BASE)/include
+INCLUDES += -I$(ENV_DIR)
+INCLUDES += -I$(PLATFORM_DIR)
+
+CC := $(BSP_BASE)/../toolchain/bin/riscv32-unknown-elf-gcc
+
+LDFLAGS += -T $(LINKER_SCRIPT) -nostdlib -nostartfiles -lc -lgcc
+LDFLAGS += -L$(ENV_DIR)
+
+ASM_OBJS := $(patsubst %.S,%.o,$(ASM_SRCS))
+C_OBJS := $(patsubst %.c,%.o,$(C_SRCS))
+
+LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
+
+CFLAGS += -g
+
+$(TARGET): $(LINK_OBJS) $(LINKER_SCRIPT)
+ $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS)
+
+$(ASM_OBJS): %.o: %.S $(HEADERS)
+ $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
+
+$(C_OBJS): %.o: %.c $(HEADERS)
+ $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
+
+all: $(TARGET)
+
+clean:
+ rm -f $(TARGET) $(LINK_OBJS)
+
+.PHONY: all clean
diff --git a/bsp/env/encoding.h b/bsp/env/encoding.h
new file mode 100644
index 0000000..35e0f9f
--- /dev/null
+++ b/bsp/env/encoding.h
@@ -0,0 +1,1313 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_PUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_VM 0x1F000000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_PUM 0x00040000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define VM_MBARE 0
+#define VM_MBB 1
+#define VM_MBBID 2
+#define VM_SV32 8
+#define VM_SV39 9
+#define VM_SV48 10
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define DEFAULT_NMIVEC 0x00001004
+#define DEFAULT_MTVEC 0x00001010
+#define CONFIG_STRING_ADDR 0x0000100C
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#ifdef __riscv64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+ else \
+ asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
+ else \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
+ else \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_HRET 0x20200073
+#define MASK_HRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VM 0x10400073
+#define MASK_SFENCE_VM 0xfff07fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_SBADADDR 0x143
+#define CSR_SIP 0x144
+#define CSR_SPTBR 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MBADADDR 0x343
+#define CSR_MIP 0x344
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MUCOUNTEREN 0x320
+#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FAULT_FETCH 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_FAULT_LOAD 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_FAULT_STORE 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(sptbr, CSR_SPTBR)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+#endif
diff --git a/bsp/env/freedom-e300-arty/entry.S b/bsp/env/freedom-e300-arty/entry.S
new file mode 100644
index 0000000..c8ec662
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/entry.S
@@ -0,0 +1,81 @@
+/*-
+ * Copyright (c) 2013-2015 Marko Zec, University of Zagreb
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+
+/*
+ * Copy data, clear BSS, set small data index register and jump into main().
+ *
+ * Assumes that the loader has already properly:
+ * 1) set stack pointer
+ * 2) set return address
+ * 3) invalidated caches
+ */
+
+ .section .init
+ .globl _start
+ .type _start,@function
+
+_start:
+ la gp, _gp
+ la sp, _sp
+
+ /* Load data sections */
+ la s0, _data
+ la s1, _edata
+ la s2, _data_lma
+ j 2f
+1:
+ lw t0, (s2)
+ sw t0, (s0)
+ addi s2, s2, 4
+ addi s0, s0, 4
+2:
+ bltu s0, s1, 1b
+
+ la s1, _end /* End of BSS section, word aligned */
+ la s0, __bss_start /* Start of BSS section, word aligned */
+ j bss_bzero_enter
+
+ /* The loader doesn't bzero the BSS, so we must do it here. */
+bss_bzero_loop:
+ sw zero, (s0)
+ addi s0, s0, 4
+bss_bzero_enter:
+ bne s0, s1, bss_bzero_loop
+
+ la s0, __init_array_start
+ la s1, __init_array_end
+ move s2, ra
+ j ctor_loop_enter
+
+ctor_loop:
+ lw a0, (s0)
+ addi s0, s0, 4
+ jalr a0
+ctor_loop_enter:
+ bne s0, s1, ctor_loop
+ move ra, s2
+ j _init
diff --git a/bsp/env/freedom-e300-arty/init.c b/bsp/env/freedom-e300-arty/init.c
new file mode 100644
index 0000000..36272f7
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/init.c
@@ -0,0 +1,61 @@
+#include <stdint.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+extern int main(int argc, char** argv);
+
+uint32_t get_cpu_freq()
+{
+ return 65000000;
+}
+
+static void uart_init(size_t baud_rate)
+{
+ GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+ GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+ UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+ UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+ if (0){
+#ifdef USE_PLIC
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+ handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+ handle_m_time_interrupt();
+#endif
+ }
+ else {
+ write(1, "trap\n", 5);
+ _exit(1 + mcause);
+ }
+ return epc;
+}
+
+void _init()
+{
+ uart_init(115200);
+
+ printf("core freq at %d Hz\n", get_cpu_freq());
+
+ write_csr(mtvec, &handle_trap);
+
+ _exit(main(0, NULL));
+}
diff --git a/bsp/env/freedom-e300-arty/link.lds b/bsp/env/freedom-e300-arty/link.lds
new file mode 100644
index 0000000..e25baf4
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/link.lds
@@ -0,0 +1,163 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+ flash PT_LOAD;
+ ram_init PT_LOAD;
+ ram PT_NULL;
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash :flash
+
+ .text :
+ {
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash :flash
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash :flash
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >flash AT>flash :flash
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ } >flash AT>flash :flash
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data = . );
+ } >ram AT>flash :ram_init
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >ram AT>flash :ram_init
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >ram AT>flash :ram_init
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ } >ram AT>flash :ram_init
+
+ .srodata :
+ {
+ PROVIDE( _gp = . + 0x800 );
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash :ram_init
+
+ .sdata :
+ {
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ } >ram AT>flash :ram_init
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram :ram
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram :ram
+}
diff --git a/bsp/env/freedom-e300-arty/openocd.cfg b/bsp/env/freedom-e300-arty/openocd.cfg
new file mode 100644
index 0000000..251dc52
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/openocd.cfg
@@ -0,0 +1,16 @@
+adapter_khz 10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset
+halt
+#flash protect 0 64 last off
diff --git a/bsp/env/freedom-e300-arty/platform.h b/bsp/env/freedom-e300-arty/platform.h
new file mode 100644
index 0000000..c408ac4
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/platform.h
@@ -0,0 +1,119 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+#define MCAUSE_INT 0x80000000
+#define MCAUSE_CAUSE 0x7FFFFFFF
+
+#include "sifive/const.h"
+#include "sifive/devices/aon.h"
+#include "sifive/devices/clint.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/plic.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
+#define CLINT_BASE_ADDR _AC(0x02000000,UL)
+#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
+#define AON_BASE_ADDR _AC(0x10000000,UL)
+#define GPIO_BASE_ADDR _AC(0x10012000,UL)
+#define UART0_BASE_ADDR _AC(0x10013000,UL)
+#define SPI0_BASE_ADDR _AC(0x10014000,UL)
+#define PWM0_BASE_ADDR _AC(0x10015000,UL)
+#define UART1_BASE_ADDR _AC(0x10023000,UL)
+#define SPI1_BASE_ADDR _AC(0x10024000,UL)
+#define PWM1_BASE_ADDR _AC(0x10025000,UL)
+#define SPI2_BASE_ADDR _AC(0x10034000,UL)
+#define PWM2_BASE_ADDR _AC(0x10035000,UL)
+#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
+#define MEM_BASE_ADDR _AC(0x80000000,UL)
+
+// IOF Mappings
+#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
+#define SPI11_NUM_SS (4)
+#define IOF_SPI1_SS0 (2u)
+#define IOF_SPI1_SS1 (8u)
+#define IOF_SPI1_SS2 (9u)
+#define IOF_SPI1_SS3 (10u)
+#define IOF_SPI1_MOSI (3u)
+#define IOF_SPI1_MISO (4u)
+#define IOF_SPI1_SCK (5u)
+#define IOF_SPI1_DQ0 (3u)
+#define IOF_SPI1_DQ1 (4u)
+#define IOF_SPI1_DQ2 (6u)
+#define IOF_SPI1_DQ3 (7u)
+
+#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
+#define SPI2_NUM_SS (1)
+#define IOF_SPI2_SS0 (26u)
+#define IOF_SPI2_MOSI (27u)
+#define IOF_SPI2_MISO (28u)
+#define IOF_SPI2_SCK (29u)
+#define IOF_SPI2_DQ0 (27u)
+#define IOF_SPI2_DQ1 (28u)
+#define IOF_SPI2_DQ2 (30u)
+#define IOF_SPI2_DQ3 (31u)
+
+#define IOF0_UART0_MASK _AC(0x00030000, UL)
+#define IOF_UART0_RX (16u)
+#define IOF_UART0_TX (17u)
+
+#define IOF0_UART1_MASK _AC(0x03000000, UL)
+#define IOF_UART1_RX (24u)
+#define IOF_UART1_TX (25u)
+
+#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
+#define IOF1_PWM1_MASK _AC(0x00780000, UL)
+#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
+
+// Interrupt Numbers
+#define INT_RESERVED 0
+#define INT_WDOGCMP 1
+#define INT_RTCCMP 2
+#define INT_UART0_BASE 3
+#define INT_UART1_BASE 4
+#define INT_SPI0_BASE 5
+#define INT_SPI1_BASE 6
+#define INT_SPI2_BASE 7
+#define INT_GPIO_BASE 8
+#define INT_PWM0_BASE 40
+#define INT_PWM1_BASE 44
+#define INT_PWM2_BASE 48
+
+// Helper functions
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
+#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
+#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
+
+// Misc
+
+#include <stdint.h>
+
+#define PLIC_NUM_INTERRUPTS 52
+#define PLIC_NUM_PRIORITIES 7
+
+#define HAS_BOARD_BUTTONS
+#include "hifive1.h"
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/freedom-e300-hifive1/entry.S b/bsp/env/freedom-e300-hifive1/entry.S
new file mode 100644
index 0000000..c8ec662
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/entry.S
@@ -0,0 +1,81 @@
+/*-
+ * Copyright (c) 2013-2015 Marko Zec, University of Zagreb
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+
+/*
+ * Copy data, clear BSS, set small data index register and jump into main().
+ *
+ * Assumes that the loader has already properly:
+ * 1) set stack pointer
+ * 2) set return address
+ * 3) invalidated caches
+ */
+
+ .section .init
+ .globl _start
+ .type _start,@function
+
+_start:
+ la gp, _gp
+ la sp, _sp
+
+ /* Load data sections */
+ la s0, _data
+ la s1, _edata
+ la s2, _data_lma
+ j 2f
+1:
+ lw t0, (s2)
+ sw t0, (s0)
+ addi s2, s2, 4
+ addi s0, s0, 4
+2:
+ bltu s0, s1, 1b
+
+ la s1, _end /* End of BSS section, word aligned */
+ la s0, __bss_start /* Start of BSS section, word aligned */
+ j bss_bzero_enter
+
+ /* The loader doesn't bzero the BSS, so we must do it here. */
+bss_bzero_loop:
+ sw zero, (s0)
+ addi s0, s0, 4
+bss_bzero_enter:
+ bne s0, s1, bss_bzero_loop
+
+ la s0, __init_array_start
+ la s1, __init_array_end
+ move s2, ra
+ j ctor_loop_enter
+
+ctor_loop:
+ lw a0, (s0)
+ addi s0, s0, 4
+ jalr a0
+ctor_loop_enter:
+ bne s0, s1, ctor_loop
+ move ra, s2
+ j _init
diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c
new file mode 100644
index 0000000..d085f6c
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/init.c
@@ -0,0 +1,187 @@
+#include <stdint.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+uint32_t cpu_freq = 0;
+
+extern int main(int argc, char** argv);
+
+uint32_t mtime_lo(void)
+{
+ return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME);
+}
+
+uint32_t mcycle_lo(void)
+{
+ uint32_t t;
+ asm volatile ("csrr %0, mcycle" : "=r" (t));
+ return t;
+}
+
+static void use_hfrosc(int div, int trim)
+{
+ // Make sure the HFROSC is running at its default setting
+ PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+ while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+static void use_pll(int refsel, int bypass, int r, int f, int q)
+{
+ // Ensure that we aren't running off the PLL before we mess with it.
+ if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+ // Make sure the HFROSC is running at its default setting
+ use_hfrosc(4, 16);
+ }
+
+ // Set PLL Source to be HFXOSC if available.
+ uint32_t config_value = 0;
+
+ config_value |= PLL_REFSEL(refsel);
+
+ if (bypass) {
+ // Bypass
+ config_value |= PLL_BYPASS(1);
+
+ PRCI_REG(PRCI_PLLCFG) = config_value;
+
+ // If we don't have an HFXTAL, this doesn't really matter.
+ // Set our Final output divide to divide-by-1:
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+ } else {
+ // In case we are executing from QSPI,
+ // (which is quite likely) we need to
+ // set the QSPI clock divider appropriately
+ // before boosting the clock frequency.
+
+ // Div = f_sck/2
+ SPI0_REG(SPI_REG_SCKDIV) = 8;
+
+ // Set DIV Settings for PLL
+ // Both HFROSC and HFXOSC are modeled as ideal
+ // 16MHz sources (assuming dividers are set properly for
+ // HFROSC).
+ // (Legal values of f_REF are 6-48MHz)
+
+ // Set DIVR to divide-by-2 to get 8MHz frequency
+ // (legal values of f_R are 6-12 MHz)
+
+ config_value |= PLL_BYPASS(1);
+ config_value |= PLL_R(r);
+
+ // Set DIVF to get 512Mhz frequncy
+ // There is an implied multiply-by-2, 16Mhz.
+ // So need to write 32-1
+ // (legal values of f_F are 384-768 MHz)
+ config_value |= PLL_F(f);
+
+ // Set DIVQ to divide-by-2 to get 256 MHz frequency
+ // (legal values of f_Q are 50-400Mhz)
+ config_value |= PLL_Q(q);
+
+ // Set our Final output divide to divide-by-1:
+ PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+
+ PRCI_REG(PRCI_PLLCFG) = config_value;
+
+ // Un-Bypass the PLL.
+ PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+ // Wait for PLL Lock
+ // Note that the Lock signal can be glitchy.
+ // Need to wait 100 us
+ // RTC is running at 32kHz.
+ // So wait 4 ticks of RTC.
+ uint32_t now = mtime_lo();
+ while (mtime_lo() - now < 4) ;
+
+ // Now it is safe to check for PLL Lock
+ while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
+ }
+
+ // Switch over to PLL Clock source
+ PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+}
+
+static void use_default_clocks()
+{
+ // Turn off the LFROSC
+ AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+ // Use HFROSC
+ use_hfrosc(4, 16);
+}
+
+void measure_cpu_freq(size_t n, size_t mtime_freq)
+{
+ uint32_t start_mtime = mtime_lo();
+ uint32_t start_mcycle = mcycle_lo();
+
+ while (mtime_lo() - start_mtime < n) ;
+
+ uint32_t end_mtime = mtime_lo();
+ uint32_t end_mcycle = mcycle_lo();
+
+ cpu_freq = (end_mcycle-start_mcycle)/n*mtime_freq;
+}
+
+uint32_t get_cpu_freq()
+{
+ return cpu_freq;
+}
+
+static void uart_init(size_t baud_rate)
+{
+ GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+ GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+ UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+ UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+ if (0){
+#ifdef USE_PLIC
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+ handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+ // External Machine-Level interrupt from PLIC
+ } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+ handle_m_time_interrupt();
+#endif
+ }
+ else {
+ write(1, "trap\n", 5);
+ _exit(1 + mcause);
+ }
+ return epc;
+}
+
+
+void _init()
+{
+ use_default_clocks();
+ use_pll(0, 0, 1, 31, 1);
+ measure_cpu_freq(1000, 32768);
+ uart_init(115200);
+
+ printf("core freq at %d Hz\n", get_cpu_freq());
+
+ write_csr(mtvec, &handle_trap);
+
+ _exit(main(0, NULL));
+}
diff --git a/bsp/env/freedom-e300-hifive1/link.lds b/bsp/env/freedom-e300-hifive1/link.lds
new file mode 100644
index 0000000..e25baf4
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/link.lds
@@ -0,0 +1,163 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+PHDRS
+{
+ flash PT_LOAD;
+ ram_init PT_LOAD;
+ ram PT_NULL;
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash :flash
+
+ .text :
+ {
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash :flash
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash :flash
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >flash AT>flash :flash
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ } >flash AT>flash :flash
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data = . );
+ } >ram AT>flash :ram_init
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >ram AT>flash :ram_init
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >ram AT>flash :ram_init
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >ram AT>flash :ram_init
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ } >ram AT>flash :ram_init
+
+ .srodata :
+ {
+ PROVIDE( _gp = . + 0x800 );
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash :ram_init
+
+ .sdata :
+ {
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ } >ram AT>flash :ram_init
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram :ram
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ } >ram AT>ram :ram
+}
diff --git a/bsp/env/freedom-e300-hifive1/openocd.cfg b/bsp/env/freedom-e300-hifive1/openocd.cfg
new file mode 100644
index 0000000..9a260ed
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/openocd.cfg
@@ -0,0 +1,21 @@
+adapter_khz 10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset
+halt
+flash protect 0 64 last off
diff --git a/bsp/env/freedom-e300-hifive1/platform.h b/bsp/env/freedom-e300-hifive1/platform.h
new file mode 100644
index 0000000..f0c763a
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/platform.h
@@ -0,0 +1,129 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+#define MCAUSE_INT 0x80000000
+#define MCAUSE_CAUSE 0x7FFFFFFF
+
+#include "sifive/const.h"
+#include "sifive/devices/aon.h"
+#include "sifive/devices/clint.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/otp.h"
+#include "sifive/devices/plic.h"
+#include "sifive/devices/prci.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+// Memory map
+#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
+#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
+#define OTP_MMAP_ADDR _AC(0x00020000,UL)
+#define CLINT_BASE_ADDR _AC(0x02000000,UL)
+#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
+#define AON_BASE_ADDR _AC(0x10000000,UL)
+#define PRCI_BASE_ADDR _AC(0x10008000,UL)
+#define OTP_BASE_ADDR _AC(0x10010000,UL)
+#define GPIO_BASE_ADDR _AC(0x10012000,UL)
+#define UART0_BASE_ADDR _AC(0x10013000,UL)
+#define SPI0_BASE_ADDR _AC(0x10014000,UL)
+#define PWM0_BASE_ADDR _AC(0x10015000,UL)
+#define UART1_BASE_ADDR _AC(0x10023000,UL)
+#define SPI1_BASE_ADDR _AC(0x10024000,UL)
+#define PWM1_BASE_ADDR _AC(0x10025000,UL)
+#define SPI2_BASE_ADDR _AC(0x10034000,UL)
+#define PWM2_BASE_ADDR _AC(0x10035000,UL)
+#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
+#define MEM_BASE_ADDR _AC(0x80000000,UL)
+
+// IOF masks
+#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
+#define SPI11_NUM_SS (4)
+#define IOF_SPI1_SS0 (2u)
+#define IOF_SPI1_SS1 (8u)
+#define IOF_SPI1_SS2 (9u)
+#define IOF_SPI1_SS3 (10u)
+#define IOF_SPI1_MOSI (3u)
+#define IOF_SPI1_MISO (4u)
+#define IOF_SPI1_SCK (5u)
+#define IOF_SPI1_DQ0 (3u)
+#define IOF_SPI1_DQ1 (4u)
+#define IOF_SPI1_DQ2 (6u)
+#define IOF_SPI1_DQ3 (7u)
+
+#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
+#define SPI2_NUM_SS (1)
+#define IOF_SPI2_SS0 (26u)
+#define IOF_SPI2_MOSI (27u)
+#define IOF_SPI2_MISO (28u)
+#define IOF_SPI2_SCK (29u)
+#define IOF_SPI2_DQ0 (27u)
+#define IOF_SPI2_DQ1 (28u)
+#define IOF_SPI2_DQ2 (30u)
+#define IOF_SPI2_DQ3 (31u)
+
+//#define IOF0_I2C_MASK _AC(0x00003000,UL)
+
+#define IOF0_UART0_MASK _AC(0x00030000, UL)
+#define IOF_UART0_RX (16u)
+#define IOF_UART0_TX (17u)
+
+#define IOF0_UART1_MASK _AC(0x03000000, UL)
+#define IOF_UART1_RX (24u)
+#define IOF_UART1_TX (25u)
+
+#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
+#define IOF1_PWM1_MASK _AC(0x00780000, UL)
+#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
+
+// Interrupt numbers
+#define INT_RESERVED 0
+#define INT_WDOGCMP 1
+#define INT_RTCCMP 2
+#define INT_UART0_BASE 3
+#define INT_UART1_BASE 4
+#define INT_SPI0_BASE 5
+#define INT_SPI1_BASE 6
+#define INT_SPI2_BASE 7
+#define INT_GPIO_BASE 8
+#define INT_PWM0_BASE 40
+#define INT_PWM1_BASE 44
+#define INT_PWM2_BASE 48
+
+// Helper functions
+#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
+#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
+#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
+#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
+#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
+#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
+#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
+#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
+#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
+#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
+#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
+#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
+
+// Misc
+
+#include <stdint.h>
+
+#define PLIC_NUM_INTERRUPTS 52
+#define PLIC_NUM_PRIORITIES 7
+
+#include "hifive1.h"
+
+uint32_t get_cpu_freq();
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/hifive1.h b/bsp/env/hifive1.h
new file mode 100644
index 0000000..f6bef9f
--- /dev/null
+++ b/bsp/env/hifive1.h
@@ -0,0 +1,81 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_HIFIVE1_H
+#define _SIFIVE_HIFIVE1_H
+
+#include <stdint.h>
+
+/****************************************************************************
+ * GPIO Connections
+ *****************************************************************************/
+
+// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
+// These are also mapped to RGB LEDs on the Freedom E300 Arty
+// FPGA
+// Dev Kit.
+
+#define RED_LED_OFFSET 22
+#define GREEN_LED_OFFSET 19
+#define BLUE_LED_OFFSET 21
+
+// These are the GPIO bit offsets for the differen digital pins
+// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
+#define PIN_0_OFFSET 16
+#define PIN_1_OFFSET 17
+#define PIN_2_OFFSET 18
+#define PIN_3_OFFSET 19
+#define PIN_4_OFFSET 20
+#define PIN_5_OFFSET 21
+#define PIN_6_OFFSET 22
+#define PIN_7_OFFSET 23
+#define PIN_8_OFFSET 0
+#define PIN_9_OFFSET 1
+#define PIN_10_OFFSET 2
+#define PIN_11_OFFSET 3
+#define PIN_12_OFFSET 4
+#define PIN_13_OFFSET 5
+//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
+#define PIN_15_OFFSET 9
+#define PIN_16_OFFSET 10
+#define PIN_17_OFFSET 11
+#define PIN_18_OFFSET 12
+#define PIN_19_OFFSET 13
+
+// These are *PIN* numbers, not
+// GPIO Offset Numbers.
+#define PIN_SPI1_SCK (13u)
+#define PIN_SPI1_MISO (12u)
+#define PIN_SPI1_MOSI (11u)
+#define PIN_SPI1_SS0 (10u)
+#define PIN_SPI1_SS1 (14u)
+#define PIN_SPI1_SS2 (15u)
+#define PIN_SPI1_SS3 (16u)
+
+#define SS_PIN_TO_CS_ID(x) \
+ ((x==PIN_SPI1_SS0 ? 0 : \
+ (x==PIN_SPI1_SS1 ? 1 : \
+ (x==PIN_SPI1_SS2 ? 2 : \
+ (x==PIN_SPI1_SS3 ? 3 : \
+ -1)))))
+
+
+// These buttons are present only on the Freedom E300 Arty Dev Kit.
+#ifdef HAS_BOARD_BUTTONS
+#define BUTTON_0_OFFSET 15
+#define BUTTON_1_OFFSET 30
+#define BUTTON_2_OFFSET 31
+
+#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_0_OFFSET)
+
+#endif
+
+#define HAS_HFXOSC 1
+#define HAS_LFROSC_BYPASS 1
+
+
+
+void write_hex(int fd, uint32_t hex);
+
+#endif /* _SIFIVE_HIFIVE1_H */
diff --git a/software/shared/syscall.c b/bsp/env/syscall.c
index 1acb88f..1b5de50 100644
--- a/software/shared/syscall.c
+++ b/bsp/env/syscall.c
@@ -14,58 +14,51 @@
#include <stdio.h>
#include <string.h>
-#include "encoding.h"
+#include "platform.h"
-#include "shared.h"
-
-volatile uint64_t tohost __attribute__((aligned(64)));
-volatile uint64_t fromhost __attribute__((aligned(64)));
-
-void write_hex(int fd, uint32_t hex){
+void write_hex(int fd, uint32_t hex)
+{
uint8_t ii;
uint8_t jj;
char towrite;
- write( fd , "0x", 2 );
- for (ii = 8 ; ii > 0; ii--){
- jj = ii-1;
+ write(fd , "0x", 2);
+ for (ii = 8 ; ii > 0; ii--) {
+ jj = ii - 1;
uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4));
towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA));
- write( fd, &towrite, 1);
+ write(fd, &towrite, 1);
}
-
}
-
void _exit(int code)
{
- volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
+ //volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
const char * message = "\nProgam has exited with code:";
- *leds = (~(code));
+ //*leds = (~(code));
write(STDERR_FILENO, message, strlen(message));
write_hex(STDERR_FILENO, code);
+ write(STDERR_FILENO, "\n", 1);
- while (1){};
-
+ while (1) ;
}
void *sbrk(ptrdiff_t incr)
{
- // extern char _end[];
- // extern char _heap_end[];
- // static char *curbrk = _end;
+ extern char _end[];
+ extern char _heap_end[];
+ static char *curbrk = _end;
- // if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+ if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1;
- // curbrk += incr;
- //return curbrk - incr;
+ curbrk += incr;
+ return curbrk - incr;
}
static int stub(int err)
{
- errno = err;
return -1;
}
@@ -114,7 +107,6 @@ int isatty(int fd)
if (fd == STDOUT_FILENO || fd == STDERR_FILENO)
return 1;
- errno = EBADF;
return 0;
}
@@ -138,23 +130,20 @@ off_t lseek(int fd, off_t ptr, int dir)
ssize_t read(int fd, void* ptr, size_t len)
{
- int i;
- uint8_t * current = (uint8_t*) ptr;
- volatile uint8_t * uart_rx = (uint8_t*) (UART_BASE_ADDR + UART_RX_OFFSET);
- volatile uint32_t * uart_rx_cnt = (uint32_t*) (UART_BASE_ADDR + UART_RX_COUNT_OFFSET);
+ uint8_t * current = (uint8_t *)ptr;
+ volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO);
+ volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2);
ssize_t result = 0;
if (isatty(fd)) {
-
- for (current = (uint8_t*) ptr;
- (current < ((uint8_t*) ptr) + len) && (*uart_rx_cnt > 0);
- current ++){
+ for (current = (uint8_t *)ptr;
+ (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0);
+ current ++) {
*current = *uart_rx;
- result ++;
+ result++;
}
return result;
-
}
return stub(EBADF);
@@ -182,25 +171,20 @@ int wait(int* status)
ssize_t write(int fd, const void* ptr, size_t len)
{
+ const uint8_t * current = (const char *)ptr;
- const uint8_t * current = (const char*) ptr;
- volatile uint32_t * uart_tx_count = (uint32_t*) (UART_BASE_ADDR + UART_TX_COUNT_OFFSET);
- volatile uint8_t * uart_tx = (uint8_t*) (UART_BASE_ADDR + UART_TX_OFFSET);
-
- size_t jj;
if (isatty(fd)) {
-
- for (jj = 0; jj < len; jj++){
+ for (size_t jj = 0; jj < len; jj++) {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = current[jj];
- while ((*uart_tx_count) < 1){};
- *uart_tx = current[jj];
-
- if (current[jj] == '\n'){
- while ((*uart_tx_count) < 1){};
- *uart_tx = '\r';
+ if (current[jj] == '\n') {
+ while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
+ UART0_REG(UART_REG_TXFIFO) = '\r';
}
}
return len;
}
+
return stub(EBADF);
}
diff --git a/bsp/include/sifive/bits.h b/bsp/include/sifive/bits.h
new file mode 100644
index 0000000..e550f80
--- /dev/null
+++ b/bsp/include/sifive/bits.h
@@ -0,0 +1,35 @@
+#ifndef _RISCV_BITS_H
+#define _RISCV_BITS_H
+
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+
+#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
+#define ROUNDDOWN(a, b) ((a)/(b)*(b))
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
+
+#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
+#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#define STR(x) XSTR(x)
+#define XSTR(x) #x
+
+#ifdef __riscv64
+# define SLL32 sllw
+# define STORE sd
+# define LOAD ld
+# define LWU lwu
+# define LOG_REGBYTES 3
+#else
+# define SLL32 sll
+# define STORE sw
+# define LOAD lw
+# define LWU lw
+# define LOG_REGBYTES 2
+#endif
+#define REGBYTES (1 << LOG_REGBYTES)
+
+#endif
diff --git a/bsp/include/sifive/const.h b/bsp/include/sifive/const.h
new file mode 100644
index 0000000..3e0a681
--- /dev/null
+++ b/bsp/include/sifive/const.h
@@ -0,0 +1,17 @@
+/* Derived from <linux/const.h> */
+
+#ifndef _SIFIVE_CONST_H
+#define _SIFIVE_CONST_H
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y) X
+#define _AT(T,X) X
+#else
+#define _AC(X,Y) (X##Y)
+#define _AT(T,X) ((T)(X))
+#endif /* !__ASSEMBLER__*/
+
+#define _BITUL(x) (_AC(1,UL) << (x))
+#define _BITULL(x) (_AC(1,ULL) << (x))
+
+#endif /* _SIFIVE_CONST_H */
diff --git a/bsp/include/sifive/devices/aon.h b/bsp/include/sifive/devices/aon.h
new file mode 100644
index 0000000..63f1db3
--- /dev/null
+++ b/bsp/include/sifive/devices/aon.h
@@ -0,0 +1,88 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_AON_H
+#define _SIFIVE_AON_H
+
+/* Register offsets */
+
+#define AON_WDOGCFG 0x000
+#define AON_WDOGCOUNT 0x008
+#define AON_WDOGS 0x010
+#define AON_WDOGFEED 0x018
+#define AON_WDOGKEY 0x01C
+#define AON_WDOGCMP 0x020
+
+#define AON_RTCCFG 0x040
+#define AON_RTCLO 0x048
+#define AON_RTCHI 0x04C
+#define AON_RTCS 0x050
+#define AON_RTCCMP 0x060
+
+#define AON_BACKUP0 0x080
+#define AON_BACKUP1 0x084
+#define AON_BACKUP2 0x088
+#define AON_BACKUP3 0x08C
+#define AON_BACKUP4 0x090
+#define AON_BACKUP5 0x094
+#define AON_BACKUP6 0x098
+#define AON_BACKUP7 0x09C
+#define AON_BACKUP8 0x0A0
+#define AON_BACKUP9 0x0A4
+#define AON_BACKUP10 0x0A8
+#define AON_BACKUP11 0x0AC
+#define AON_BACKUP12 0x0B0
+#define AON_BACKUP13 0x0B4
+#define AON_BACKUP14 0x0B8
+#define AON_BACKUP15 0x0BC
+
+#define AON_PMUWAKEUPI0 0x100
+#define AON_PMUWAKEUPI1 0x104
+#define AON_PMUWAKEUPI2 0x108
+#define AON_PMUWAKEUPI3 0x10C
+#define AON_PMUWAKEUPI4 0x110
+#define AON_PMUWAKEUPI5 0x114
+#define AON_PMUWAKEUPI6 0x118
+#define AON_PMUWAKEUPI7 0x11C
+#define AON_PMUSLEEPI0 0x120
+#define AON_PMUSLEEPI1 0x124
+#define AON_PMUSLEEPI2 0x128
+#define AON_PMUSLEEPI3 0x12C
+#define AON_PMUSLEEPI4 0x130
+#define AON_PMUSLEEPI5 0x134
+#define AON_PMUSLEEPI6 0x138
+#define AON_PMUSLEEPI7 0x13C
+#define AON_PMUIE 0x140
+#define AON_PMUCAUSE 0x144
+#define AON_PMUSLEEP 0x148
+#define AON_PMUKEY 0x14C
+
+#define AON_LFROSC 0x070
+/* Constants */
+
+#define AON_WDOGKEY_VALUE 0x51F15E
+#define AON_WDOGFEED_VALUE 0xD09F00D
+
+#define AON_WDOGCFG_SCALE 0x0000000F
+#define AON_WDOGCFG_RSTEN 0x00000100
+#define AON_WDOGCFG_ZEROCMP 0x00000200
+#define AON_WDOGCFG_ENALWAYS 0x00001000
+#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
+#define AON_WDOGCFG_CMPIP 0x10000000
+
+#define AON_RTCCFG_SCALE 0x0000000F
+#define AON_RTCCFG_ENALWAYS 0x00001000
+#define AON_RTCCFG_CMPIP 0x10000000
+
+#define AON_WAKEUPCAUSE_RESET 0x00
+#define AON_WAKEUPCAUSE_RTC 0x01
+#define AON_WAKEUPCAUSE_DWAKEUP 0x02
+#define AON_WAKEUPCAUSE_AWAKEUP 0x03
+
+#define AON_RESETCAUSE_POWERON 0x0000
+#define AON_RESETCAUSE_EXTERNAL 0x0100
+#define AON_RESETCAUSE_WATCHDOG 0x0200
+
+#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
+#define AON_PMUCAUSE_RESETCAUSE 0xFF00
+
+#endif /* _SIFIVE_AON_H */
diff --git a/bsp/include/sifive/devices/clint.h b/bsp/include/sifive/devices/clint.h
new file mode 100644
index 0000000..cd3e0c7
--- /dev/null
+++ b/bsp/include/sifive/devices/clint.h
@@ -0,0 +1,14 @@
+// See LICENSE for license details
+
+#ifndef _SIFIVE_CLINT_H
+#define _SIFIVE_CLINT_H
+
+
+#define CLINT_MSIP 0x0000
+#define CLINT_MSIP_size 0x4
+#define CLINT_MTIMECMP 0x4000
+#define CLINT_MTIMECMP_size 0x8
+#define CLINT_MTIME 0xBFF8
+#define CLINT_MTIME_size 0x8
+
+#endif /* _SIFIVE_CLINT_H */
diff --git a/bsp/include/sifive/devices/gpio.h b/bsp/include/sifive/devices/gpio.h
new file mode 100644
index 0000000..f7f0acb
--- /dev/null
+++ b/bsp/include/sifive/devices/gpio.h
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_GPIO_H
+#define _SIFIVE_GPIO_H
+
+#define GPIO_INPUT_VAL (0x00)
+#define GPIO_INPUT_EN (0x04)
+#define GPIO_OUTPUT_EN (0x08)
+#define GPIO_OUTPUT_VAL (0x0C)
+#define GPIO_PULLUP_EN (0x10)
+#define GPIO_DRIVE (0x14)
+#define GPIO_RISE_IE (0x18)
+#define GPIO_RISE_IP (0x1C)
+#define GPIO_FALL_IE (0x20)
+#define GPIO_FALL_IP (0x24)
+#define GPIO_HIGH_IE (0x28)
+#define GPIO_HIGH_IP (0x2C)
+#define GPIO_LOW_IE (0x30)
+#define GPIO_LOW_IP (0x34)
+#define GPIO_IOF_EN (0x38)
+#define GPIO_IOF_SEL (0x3C)
+#define GPIO_OUTPUT_XOR (0x40)
+
+#endif /* _SIFIVE_GPIO_H */
diff --git a/bsp/include/sifive/devices/otp.h b/bsp/include/sifive/devices/otp.h
new file mode 100644
index 0000000..93833e2
--- /dev/null
+++ b/bsp/include/sifive/devices/otp.h
@@ -0,0 +1,23 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_OTP_H
+#define _SIFIVE_OTP_H
+
+/* Register offsets */
+
+#define OTP_LOCK 0x00
+#define OTP_CK 0x04
+#define OTP_OE 0x08
+#define OTP_SEL 0x0C
+#define OTP_WE 0x10
+#define OTP_MR 0x14
+#define OTP_MRR 0x18
+#define OTP_MPP 0x1C
+#define OTP_VRREN 0x20
+#define OTP_VPPEN 0x24
+#define OTP_A 0x28
+#define OTP_D 0x2C
+#define OTP_Q 0x30
+#define OTP_READ_TIMINGS 0x34
+
+#endif
diff --git a/bsp/include/sifive/devices/plic.h b/bsp/include/sifive/devices/plic.h
new file mode 100644
index 0000000..e1ca5d6
--- /dev/null
+++ b/bsp/include/sifive/devices/plic.h
@@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+#ifndef PLIC_H
+#define PLIC_H
+
+#include <sifive/const.h>
+
+// 32 bits per source
+#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
+// 1 bit per source (1 address)
+#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
+#define PLIC_PENDING_SHIFT_PER_SOURCE 0
+
+//0x80 per target
+#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
+#define PLIC_ENABLE_SHIFT_PER_TARGET 7
+
+
+#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
+#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
+#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
+#define PLIC_CLAIM_SHIFT_PER_TARGET 12
+
+#define PLIC_MAX_SOURCE 1023
+#define PLIC_SOURCE_MASK 0x3FF
+
+#define PLIC_MAX_TARGET 15871
+#define PLIC_TARGET_MASK 0x3FFF
+
+#endif /* PLIC_H */
diff --git a/bsp/include/sifive/devices/prci.h b/bsp/include/sifive/devices/prci.h
new file mode 100644
index 0000000..1a3de58
--- /dev/null
+++ b/bsp/include/sifive/devices/prci.h
@@ -0,0 +1,56 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PRCI_H
+#define _SIFIVE_PRCI_H
+
+/* Register offsets */
+
+#define PRCI_HFROSCCFG (0x0000)
+#define PRCI_HFXOSCCFG (0x0004)
+#define PRCI_PLLCFG (0x0008)
+#define PRCI_PLLDIV (0x000C)
+#define PRCI_PROCMONCFG (0x00F0)
+
+/* Fields */
+#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
+#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
+#define ROSC_EN(x) (((x) & 0x1 ) << 30)
+#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
+
+#define XOSC_EN(x) (((x) & 0x1) << 30)
+#define XOSC_RDY(x) (((x) & 0x1) << 31)
+
+#define PLL_R(x) (((x) & 0x7) << 0)
+// single reserved bit for F LSB.
+#define PLL_F(x) (((x) & 0x3F) << 4)
+#define PLL_Q(x) (((x) & 0x3) << 10)
+#define PLL_SEL(x) (((x) & 0x1) << 16)
+#define PLL_REFSEL(x) (((x) & 0x1) << 17)
+#define PLL_BYPASS(x) (((x) & 0x1) << 18)
+#define PLL_LOCK(x) (((x) & 0x1) << 31)
+
+#define PLL_R_default 0x1
+#define PLL_F_default 0x1F
+#define PLL_Q_default 0x3
+
+#define PLL_REFSEL_HFROSC 0x0
+#define PLL_REFSEL_HFXOSC 0x1
+
+#define PLL_SEL_HFROSC 0x0
+#define PLL_SEL_PLL 0x1
+
+#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
+#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
+
+#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
+#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
+#define PROCMON_EN(x) (((x) & 0x1) << 16)
+#define PROCMON_SEL(x) (((x) & 0x3) << 24)
+#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
+
+#define PROCMON_SEL_HFCLK 0
+#define PROCMON_SEL_HFXOSCIN 1
+#define PROCMON_SEL_PLLOUTDIV 2
+#define PROCMON_SEL_PROCMON 3
+
+#endif // _SIFIVE_PRCI_H
diff --git a/bsp/include/sifive/devices/pwm.h b/bsp/include/sifive/devices/pwm.h
new file mode 100644
index 0000000..067889a
--- /dev/null
+++ b/bsp/include/sifive/devices/pwm.h
@@ -0,0 +1,37 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PWM_H
+#define _SIFIVE_PWM_H
+
+/* Register offsets */
+
+#define PWM_CFG 0x00
+#define PWM_COUNT 0x08
+#define PWM_S 0x10
+#define PWM_CMP0 0x20
+#define PWM_CMP1 0x24
+#define PWM_CMP2 0x28
+#define PWM_CMP3 0x2C
+
+/* Constants */
+
+#define PWM_CFG_SCALE 0x0000000F
+#define PWM_CFG_STICKY 0x00000100
+#define PWM_CFG_ZEROCMP 0x00000200
+#define PWM_CFG_DEGLITCH 0x00000400
+#define PWM_CFG_ENALWAYS 0x00001000
+#define PWM_CFG_ONESHOT 0x00002000
+#define PWM_CFG_CMP0CENTER 0x00010000
+#define PWM_CFG_CMP1CENTER 0x00020000
+#define PWM_CFG_CMP2CENTER 0x00040000
+#define PWM_CFG_CMP3CENTER 0x00080000
+#define PWM_CFG_CMP0GANG 0x01000000
+#define PWM_CFG_CMP1GANG 0x02000000
+#define PWM_CFG_CMP2GANG 0x04000000
+#define PWM_CFG_CMP3GANG 0x08000000
+#define PWM_CFG_CMP0IP 0x10000000
+#define PWM_CFG_CMP1IP 0x20000000
+#define PWM_CFG_CMP2IP 0x40000000
+#define PWM_CFG_CMP3IP 0x80000000
+
+#endif /* _SIFIVE_PWM_H */
diff --git a/bsp/include/sifive/devices/spi.h b/bsp/include/sifive/devices/spi.h
new file mode 100644
index 0000000..916d86b
--- /dev/null
+++ b/bsp/include/sifive/devices/spi.h
@@ -0,0 +1,80 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_SPI_H
+#define _SIFIVE_SPI_H
+
+/* Register offsets */
+
+#define SPI_REG_SCKDIV 0x00
+#define SPI_REG_SCKMODE 0x04
+#define SPI_REG_CSID 0x10
+#define SPI_REG_CSDEF 0x14
+#define SPI_REG_CSMODE 0x18
+
+#define SPI_REG_DCSSCK 0x28
+#define SPI_REG_DSCKCS 0x2a
+#define SPI_REG_DINTERCS 0x2c
+#define SPI_REG_DINTERXFR 0x2e
+
+#define SPI_REG_FMT 0x40
+#define SPI_REG_TXFIFO 0x48
+#define SPI_REG_RXFIFO 0x4c
+#define SPI_REG_TXCTRL 0x50
+#define SPI_REG_RXCTRL 0x54
+
+#define SPI_REG_FCTRL 0x60
+#define SPI_REG_FFMT 0x64
+
+#define SPI_REG_IE 0x70
+#define SPI_REG_IP 0x74
+
+/* Fields */
+
+#define SPI_SCK_POL 0x1
+#define SPI_SCK_PHA 0x2
+
+#define SPI_FMT_PROTO(x) ((x) & 0x3)
+#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
+#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
+#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
+
+/* TXCTRL register */
+#define SPI_TXWM(x) ((x) & 0xffff)
+/* RXCTRL register */
+#define SPI_RXWM(x) ((x) & 0xffff)
+
+#define SPI_IP_TXWM 0x1
+#define SPI_IP_RXWM 0x2
+
+#define SPI_FCTRL_EN 0x1
+
+#define SPI_INSN_CMD_EN 0x1
+#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
+#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
+#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
+#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
+#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
+#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
+#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
+
+#define SPI_TXFIFO_FULL (1 << 31)
+#define SPI_RXFIFO_EMPTY (1 << 31)
+
+/* Values */
+
+#define SPI_CSMODE_AUTO 0
+#define SPI_CSMODE_HOLD 2
+#define SPI_CSMODE_OFF 3
+
+#define SPI_DIR_RX 0
+#define SPI_DIR_TX 1
+
+#define SPI_PROTO_S 0
+#define SPI_PROTO_D 1
+#define SPI_PROTO_Q 2
+
+#define SPI_ENDIAN_MSB 0
+#define SPI_ENDIAN_LSB 1
+
+
+#endif /* _SIFIVE_SPI_H */
diff --git a/bsp/include/sifive/devices/uart.h b/bsp/include/sifive/devices/uart.h
new file mode 100644
index 0000000..71bea6f
--- /dev/null
+++ b/bsp/include/sifive/devices/uart.h
@@ -0,0 +1,27 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_UART_H
+#define _SIFIVE_UART_H
+
+/* Register offsets */
+#define UART_REG_TXFIFO 0x00
+#define UART_REG_RXFIFO 0x04
+#define UART_REG_TXCTRL 0x08
+#define UART_REG_RXCTRL 0x0c
+#define UART_REG_IE 0x10
+#define UART_REG_IP 0x14
+#define UART_REG_DIV 0x18
+
+/* TXCTRL register */
+#define UART_TXEN 0x1
+#define UART_TXWM(x) (((x) & 0xffff) << 16)
+
+/* RXCTRL register */
+#define UART_RXEN 0x1
+#define UART_RXWM(x) (((x) & 0xffff) << 16)
+
+/* IP register */
+#define UART_IP_TXWM 0x1
+#define UART_IP_RXWM 0x2
+
+#endif /* _SIFIVE_UART_H */
diff --git a/bsp/include/sifive/sections.h b/bsp/include/sifive/sections.h
new file mode 100644
index 0000000..848c237
--- /dev/null
+++ b/bsp/include/sifive/sections.h
@@ -0,0 +1,16 @@
+#ifndef _SECTIONS_H
+#define _SECTIONS_H
+
+extern unsigned char _rom[];
+extern unsigned char _rom_end[];
+
+extern unsigned char _ram[];
+extern unsigned char _ram_end[];
+
+extern unsigned char _ftext[];
+extern unsigned char _etext[];
+extern unsigned char _fbss[];
+extern unsigned char _ebss[];
+extern unsigned char _end[];
+
+#endif /* _SECTIONS_H */
diff --git a/bsp/tools/openocd_upload.sh b/bsp/tools/openocd_upload.sh
new file mode 100755
index 0000000..afa9dad
--- /dev/null
+++ b/bsp/tools/openocd_upload.sh
@@ -0,0 +1,5 @@
+#! /bin/bash -x
+
+openocd -f ${2} \
+ -c "flash protect 0 64 last off; program ${1}; resume 0x20400000; exit" \
+ 2>&1 | tee openocd_upload.log
diff --git a/openocd b/openocd
-Subproject e273e23f4158ba94c272901dc568a103aa6760b
+Subproject db2ec672b5b911ffb80732099c0ec39c7780b3c
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
-Subproject 80007506c6d284d632a08bee8526e88132ea277
+Subproject 55f83087a711a24b8704309b0dd32e6071fcafa
diff --git a/riscv-tests b/riscv-tests
deleted file mode 160000
-Subproject acb593160f2f7e22bfd6a480570f2c509463416
diff --git a/software/demo_gpio/Makefile b/software/demo_gpio/Makefile
index 5f201a2..0a0b148 100644
--- a/software/demo_gpio/Makefile
+++ b/software/demo_gpio/Makefile
@@ -1,9 +1,7 @@
-#See LICENSE for license details.
+TARGET = demo_gpio
+C_SRCS += demo_gpio.c
+C_SRCS += plic_driver.c
+CFLAGS += -fno-builtin-printf -DUSE_PLIC -DUSE_M_TIME
-TARGET=demo_gpio
-CFLAGS += -g
-CDEFINES += -DUSE_PLIC -DUSE_M_TIME
-
-SWDIR = ../
-
-include $(SWDIR)/shared/Makefile.shared
+BSP_BASE = ../../bsp
+include $(BSP_BASE)/env/common.mk
diff --git a/software/demo_gpio/demo_gpio.c b/software/demo_gpio/demo_gpio.c
index 3b0b6f5..c977281 100644
--- a/software/demo_gpio/demo_gpio.c
+++ b/software/demo_gpio/demo_gpio.c
@@ -1,10 +1,14 @@
// See LICENSE for license details.
#include <stdio.h>
-
-#include "shared.h"
-#include "plic.h"
+#include <stdlib.h>
+#include "platform.h"
#include <string.h>
+#include "plic_driver.h"
+#include "encoding.h"
+#include <unistd.h>
+
+#define RTC_FREQUENCY 32768
void reset_demo (void);
@@ -14,19 +18,19 @@ typedef void (*function_ptr_t) (void);
void no_interrupt_handler (void) {};
-function_ptr_t g_ext_interrupt_handlers[9];
+function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS];
-function_ptr_t g_m_timer_interrupt_handler = no_interrupt_handler;
// Instance data for the PLIC.
plic_instance_t g_plic;
// Simple variables for LEDs, buttons, etc.
-volatile unsigned int* g_outputs = (unsigned int *) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET);
-volatile unsigned int* g_inputs = (unsigned int *) (GPIO_BASE_ADDR + GPIO_IN_OFFSET);
-volatile unsigned int* g_tristates = (unsigned int *) (GPIO_BASE_ADDR + GPIO_TRI_OFFSET);
-
+volatile unsigned int* g_output_vals = (unsigned int *) (GPIO_BASE_ADDR + GPIO_OUTPUT_VAL);
+volatile unsigned int* g_input_vals = (unsigned int *) (GPIO_BASE_ADDR + GPIO_INPUT_VAL);
+volatile unsigned int* g_output_en = (unsigned int *) (GPIO_BASE_ADDR + GPIO_OUTPUT_EN);
+volatile unsigned int* g_pullup_en = (unsigned int *) (GPIO_BASE_ADDR + GPIO_PULLUP_EN);
+volatile unsigned int* g_input_en = (unsigned int *) (GPIO_BASE_ADDR + GPIO_INPUT_EN);
/*Entry Point for PLIC Interrupt Handler*/
void handle_m_ext_interrupt(){
@@ -35,7 +39,7 @@ void handle_m_ext_interrupt(){
g_ext_interrupt_handlers[int_num]();
}
else {
- _exit(1 + (uintptr_t) int_num);
+ exit(1 + (uintptr_t) int_num);
}
PLIC_complete_interrupt(&g_plic, int_num);
}
@@ -49,31 +53,25 @@ void handle_m_time_interrupt(){
// Reset the timer for 3s in the future.
// This also clears the existing timer interrupt.
- volatile uint64_t * mtime = (uint64_t*) MTIME_ADDR;
- volatile uint64_t * mtimecmp = (uint64_t*) MTIMECMP_BASE_ADDR;
+ volatile uint64_t * mtime = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME);
+ volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIMECMP);
uint64_t now = *mtime;
- uint64_t then = now + 3 * CLOCK_FREQUENCY / RTC_PRESCALER;
+ uint64_t then = now + 3 * RTC_FREQUENCY;
*mtimecmp = then;
// read the current value of the LEDS and invert them.
- uint32_t leds = *g_outputs;
-
- *g_outputs = (~leds) & ((0xF << RED_LEDS_OFFSET) |
- (0xF << GREEN_LEDS_OFFSET) |
- (0xF << BLUE_LEDS_OFFSET));
+ uint32_t leds = *g_output_vals;
+
+ *g_output_vals ^= ((0x1 << RED_LED_OFFSET) |
+ (0x1 << GREEN_LED_OFFSET) |
+ (0x1 << BLUE_LED_OFFSET));
-
// Re-enable the timer interrupt.
set_csr(mie, MIP_MTIP);
-
+
}
-/*Entry Point for Machine Timer Interrupt Handler*/
-void handle_m_timer_interrupt(){
- g_m_timer_interrupt_handler();
-}
-
const char * instructions_msg = " \
\n\
SIFIVE, INC.\n\
@@ -112,8 +110,10 @@ void print_instructions() {
void button_0_handler(void) {
- // Rainbow LEDs!
- * g_outputs = (0x9 << RED_LEDS_OFFSET) | (0xA << GREEN_LEDS_OFFSET) | (0xC << BLUE_LEDS_OFFSET);
+ // All LEDS on
+ * g_output_vals = (0x1 << RED_LED_OFFSET) |
+ (0x1 << GREEN_LED_OFFSET) |
+ (0x1 << BLUE_LED_OFFSET);
};
@@ -122,30 +122,31 @@ void reset_demo (){
// Disable the machine & timer interrupts until setup is done.
- clear_csr(mie, MIP_MEIP);
- clear_csr(mie, MIP_MTIP);
+ clear_csr(mie, MIP_MEIP);
+ clear_csr(mie, MIP_MTIP);
+
+ for (int ii = 0; ii < PLIC_NUM_INTERRUPTS; ii ++){
+ g_ext_interrupt_handlers[ii] = no_interrupt_handler;
+ }
+
+#ifdef HAS_BOARD_BUTTONS
+ g_ext_interrupt_handlers[INT_DEVICE_BUTTON_0] = button_0_handler;
+#endif
- g_ext_interrupt_handlers[INT_DEVICE_BUTTON_0] = button_0_handler;
- g_ext_interrupt_handlers[INT_DEVICE_BUTTON_1] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_BUTTON_2] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_BUTTON_3] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_JA_7] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_JA_8] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_JA_9] = no_interrupt_handler;
- g_ext_interrupt_handlers[INT_DEVICE_JA_10] = no_interrupt_handler;
-
- print_instructions();
+ print_instructions();
- PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_0);
-
+#ifdef HAS_BOARD_BUTTONS
+ PLIC_enable_interrupt (&g_plic, INT_DEVICE_BUTTON_0);
+#endif
+
// Set the machine timer to go off in 3 seconds.
// The
- volatile uint64_t * mtime = (uint64_t*) MTIME_ADDR;
- volatile uint64_t * mtimecmp = (uint64_t*) MTIMECMP_BASE_ADDR;
+ volatile uint64_t * mtime = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME);
+ volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIMECMP);
uint64_t now = *mtime;
- uint64_t then = now + 3*CLOCK_FREQUENCY / RTC_PRESCALER;
+ uint64_t then = now + 3*RTC_FREQUENCY;
*mtimecmp = then;
-
+
// Enable the Machine-External bit in MIE
set_csr(mie, MIP_MEIP);
@@ -154,24 +155,32 @@ void reset_demo (){
// Enable interrupts in general.
set_csr(mstatus, MSTATUS_MIE);
-
}
int main(int argc, char **argv)
{
- // Set up the GPIOs such that the inputs' tristate are set.
- // The boot ROM actually does this, but still good.
+ // Set up the GPIOs such that the LED GPIO
+ // can be used as both Inputs and Outputs.
+
+#ifdef HAS_BOARD_BUTTONS
+ * g_output_en &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x2 << BUTTON_2_OFFSET));
+ * g_pullup_en &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x2 << BUTTON_2_OFFSET));
+ * g_input_en |= ((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x2 << BUTTON_2_OFFSET));
+#endif
- * g_tristates = (0xF << BUTTONS_OFFSET) | (0xF << SWITCHES_OFFSET) | (0xF << JA_IN_OFFSET);
-
- * g_outputs = (0xF << RED_LEDS_OFFSET);
-
+ * g_input_en &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
+ * g_output_en |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
+ * g_output_vals|= (0x1 << BLUE_LED_OFFSET) ;
+ * g_output_vals &= ~((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET)) ;
/**************************************************************************
* Set up the PLIC
*
*************************************************************************/
- PLIC_init(&g_plic, PLIC_BASE_ADDR, PLIC_NUM_SOURCES, PLIC_NUM_PRIORITIES);
+ PLIC_init(&g_plic,
+ PLIC_BASE_ADDR,
+ PLIC_NUM_INTERRUPTS,
+ PLIC_NUM_PRIORITIES);
reset_demo();
diff --git a/software/shared/drivers_sifive/plic.c b/software/demo_gpio/plic_driver.c
index ec0c178..01b7e6e 100644
--- a/software/shared/drivers_sifive/plic.c
+++ b/software/demo_gpio/plic_driver.c
@@ -1,6 +1,8 @@
// See LICENSE for license details.
-#include "plic.h"
+#include "sifive/devices/plic.h"
+#include "plic_driver.h"
+#include "platform.h"
#include "encoding.h"
#include <string.h>
@@ -8,20 +10,21 @@
// Note that there are no assertions or bounds checking on these
// parameter values.
-void volatile_memzero(uint8_t * base, unsigned int size){
-
+void volatile_memzero(uint8_t * base, unsigned int size)
+{
volatile uint8_t * ptr;
for (ptr = base; ptr < (base + size); ptr++){
*ptr = 0;
}
}
-
+
void PLIC_init (
plic_instance_t * this_plic,
- uintptr_t base_addr,
+ uintptr_t base_addr,
uint32_t num_sources,
uint32_t num_priorities
- ){
+ )
+{
this_plic->base_addr = base_addr;
this_plic->num_sources = num_sources;
@@ -49,7 +52,8 @@ void PLIC_init (
}
-void PLIC_set_threshold (plic_instance_t * this_plic, plic_threshold threshold){
+void PLIC_set_threshold (plic_instance_t * this_plic,
+ plic_threshold threshold){
unsigned long hart_id = read_csr(mhartid);
volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
diff --git a/software/dhrystone/Makefile b/software/dhrystone/Makefile
new file mode 100644
index 0000000..2058ca1
--- /dev/null
+++ b/software/dhrystone/Makefile
@@ -0,0 +1,20 @@
+TARGET := dhrystone
+
+ASM_SRCS :=
+C_SRCS := dhry_stubs.c dhry_printf.c
+HEADERS := dhry.h
+
+DHRY_SRCS := dhry_1.c dhry_2.c
+DHRY_CFLAGS := -O2 -DTIME -fno-inline -Wno-implicit
+
+XLEN ?= 32
+CFLAGS := -Dscanf=dhry_scanf -Dprintf=dhry_printf -Os -fno-common
+
+DHRY_OBJS := $(patsubst %.c,%.o,$(DHRY_SRCS))
+LINK_OBJS := $(DHRY_OBJS)
+
+BSP_BASE = ../../bsp
+include $(BSP_BASE)/env/common.mk
+
+$(DHRY_OBJS): %.o: %.c $(HEADERS)
+ $(CC) $(CFLAGS) $(DHRY_CFLAGS) -c -o $@ $<
diff --git a/software/dhrystone/dhry.h b/software/dhrystone/dhry.h
new file mode 100644
index 0000000..b556ecc
--- /dev/null
+++ b/software/dhrystone/dhry.h
@@ -0,0 +1,423 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry.h (part 1 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ * Siemens AG, AUT E 51
+ * Postfach 3220
+ * 8520 Erlangen
+ * Germany (West)
+ * Phone: [+49]-9131-7-20330
+ * (8-17 Central European Time)
+ * Usenet: ..!mcsun!unido!estevax!weicker
+ *
+ * Original Version (in Ada) published in
+ * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ * pp. 1013 - 1030, together with the statistics
+ * on which the distribution of statements etc. is based.
+ *
+ * In this C version, the following C library functions are used:
+ * - strcpy, strcmp (inside the measurement loop)
+ * - printf, scanf (outside the measurement loop)
+ * In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ * are used for execution time measurement. For measurements
+ * on other systems, these calls have to be changed.
+ *
+ * Collection of Results:
+ * Reinhold Weicker (address see above) and
+ *
+ * Rick Richardson
+ * PC Research. Inc.
+ * 94 Apple Orchard Drive
+ * Tinton Falls, NJ 07724
+ * Phone: (201) 389-8963 (9-17 EST)
+ * Usenet: ...!uunet!pcrat!rick
+ *
+ * Please send results to Rick Richardson and/or Reinhold Weicker.
+ * Complete information should be given on hardware and software used.
+ * Hardware information includes: Machine type, CPU, type and size
+ * of caches; for microprocessors: clock frequency, memory speed
+ * (number of wait states).
+ * Software information includes: Compiler (and runtime library)
+ * manufacturer and version, compilation switches, OS version.
+ * The Operating System version may give an indication about the
+ * compiler; Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ * The complete output generated by the program should be mailed
+ * such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * History: This version C/2.1 has been made for two reasons:
+ *
+ * 1) There is an obvious need for a common C version of
+ * Dhrystone, since C is at present the most popular system
+ * programming language for the class of processors
+ * (microcomputers, minicomputers) where Dhrystone is used most.
+ * There should be, as far as possible, only one C version of
+ * Dhrystone such that results can be compared without
+ * restrictions. In the past, the C versions distributed
+ * by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ * had small (though not significant) differences.
+ *
+ * 2) As far as it is possible without changes to the Dhrystone
+ * statistics, optimizing compilers should be prevented from
+ * removing significant statements.
+ *
+ * This C version has been developed in cooperation with
+ * Rick Richardson (Tinton Falls, NJ), it incorporates many
+ * ideas from the "Version 1.1" distributed previously by
+ * him over the UNIX network Usenet.
+ * I also thank Chaim Benedelac (National Semiconductor),
+ * David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ * for their help with comments on earlier versions of the
+ * benchmark.
+ *
+ * Changes: In the initialization part, this version follows mostly
+ * Rick Richardson's version distributed via Usenet, not the
+ * version distributed earlier via floppy disk by Reinhold Weicker.
+ * As a concession to older compilers, names have been made
+ * unique within the first 8 characters.
+ * Inside the measurement loop, this version follows the
+ * version previously distributed by Reinhold Weicker.
+ *
+ * At several places in the benchmark, code has been added,
+ * but within the measurement loop only in branches that
+ * are not executed. The intention is that optimizing compilers
+ * should be prevented from moving code out of the measurement
+ * loop, or from removing code altogether. Since the statements
+ * that are executed within the measurement loop have NOT been
+ * changed, the numbers defining the "Dhrystone distribution"
+ * (distribution of statements, operand types and locality)
+ * still hold. Except for sophisticated optimizing compilers,
+ * execution times for this version should be the same as
+ * for previous versions.
+ *
+ * Since it has proven difficult to subtract the time for the
+ * measurement loop overhead in a correct way, the loop check
+ * has been made a part of the benchmark. This does have
+ * an impact - though a very minor one - on the distribution
+ * statistics which have been updated for this version.
+ *
+ * All changes within the measurement loop are described
+ * and discussed in the companion paper "Rationale for
+ * Dhrystone version 2".
+ *
+ * Because of the self-imposed limitation that the order and
+ * distribution of the executed statements should not be
+ * changed, there are still cases where optimizing compilers
+ * may not generate code for some statements. To a certain
+ * degree, this is unavoidable for small synthetic benchmarks.
+ * Users of the benchmark are advised to check code listings
+ * whether code is generated for all statements of Dhrystone.
+ *
+ * Version 2.1 is identical to version 2.0 distributed via
+ * the UNIX network Usenet in March 1988 except that it corrects
+ * some minor deficiencies that were found by users of version 2.0.
+ * The only change within the measurement loop is that a
+ * non-executed "else" part was added to the "if" statement in
+ * Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ ***************************************************************************
+ *
+ * Defines: The following "Defines" are possible:
+ * -DREG=register (default: Not defined)
+ * As an approximation to what an average C programmer
+ * might do, the "register" storage class is applied
+ * (if enabled by -DREG=register)
+ * - for local variables, if they are used (dynamically)
+ * five or more times
+ * - for parameters if they are used (dynamically)
+ * six or more times
+ * Note that an optimal "register" strategy is
+ * compiler-dependent, and that "register" declarations
+ * do not necessarily lead to faster execution.
+ * -DNOSTRUCTASSIGN (default: Not defined)
+ * Define if the C compiler does not support
+ * assignment of structures.
+ * -DNOENUMS (default: Not defined)
+ * Define if the C compiler does not support
+ * enumeration types.
+ * -DTIMES (default)
+ * -DTIME
+ * The "times" function of UNIX (returning process times)
+ * or the "time" function (returning wallclock time)
+ * is used for measurement.
+ * For single user machines, "time ()" is adequate. For
+ * multi-user machines where you cannot get single-user
+ * access, use the "times ()" function. If you have
+ * neither, use a stopwatch in the dead of night.
+ * "printf"s are provided marking the points "Start Timer"
+ * and "Stop Timer". DO NOT use the UNIX "time(1)"
+ * command, as this will measure the total time to
+ * run this program, which will (erroneously) include
+ * the time to allocate storage (malloc) and to perform
+ * the initialization.
+ * -DHZ=nnn
+ * In Berkeley UNIX, the function "times" returns process
+ * time in 1/HZ seconds, with HZ = 60 for most systems.
+ * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ * A VALUE.
+ *
+ ***************************************************************************
+ *
+ * Compilation model and measurement (IMPORTANT):
+ *
+ * This C version of Dhrystone consists of three files:
+ * - dhry.h (this file, containing global definitions and comments)
+ * - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ * - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ * The following "ground rules" apply for measurements:
+ * - Separate compilation
+ * - No procedure merging
+ * - Otherwise, compiler optimizations are allowed but should be indicated
+ * - Default results are those without register declarations
+ * See the companion paper "Rationale for Dhrystone Version 2" for a more
+ * detailed discussion of these ground rules.
+ *
+ * For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ * models ("small", "medium", "large" etc.) should be given if possible,
+ * together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ * Dhrystone (C version) statistics:
+ *
+ * [Comment from the first distribution, updated for version 2.
+ * Note that because of language differences, the numbers are slightly
+ * different from the Ada version.]
+ *
+ * The following program contains statements of a high level programming
+ * language (here: C) in a distribution considered representative:
+ *
+ * assignments 52 (51.0 %)
+ * control statements 33 (32.4 %)
+ * procedure, function calls 17 (16.7 %)
+ *
+ * 103 statements are dynamically executed. The program is balanced with
+ * respect to the three aspects:
+ *
+ * - statement type
+ * - operand type
+ * - operand locality
+ * operand global, local, parameter, or constant.
+ *
+ * The combination of these three aspects is balanced only approximately.
+ *
+ * 1. Statement Type:
+ * ----------------- number
+ *
+ * V1 = V2 9
+ * (incl. V1 = F(..)
+ * V = Constant 12
+ * Assignment, 7
+ * with array element
+ * Assignment, 6
+ * with record component
+ * --
+ * 34 34
+ *
+ * X = Y +|-|"&&"|"|" Z 5
+ * X = Y +|-|"==" Constant 6
+ * X = X +|- 1 3
+ * X = Y *|/ Z 2
+ * X = Expression, 1
+ * two operators
+ * X = Expression, 1
+ * three operators
+ * --
+ * 18 18
+ *
+ * if .... 14
+ * with "else" 7
+ * without "else" 7
+ * executed 3
+ * not executed 4
+ * for ... 7 | counted every time
+ * while ... 4 | the loop condition
+ * do ... while 1 | is evaluated
+ * switch ... 1
+ * break 1
+ * declaration with 1
+ * initialization
+ * --
+ * 34 34
+ *
+ * P (...) procedure call 11
+ * user procedure 10
+ * library procedure 1
+ * X = F (...)
+ * function call 6
+ * user function 5
+ * library function 1
+ * --
+ * 17 17
+ * ---
+ * 103
+ *
+ * The average number of parameters in procedure or function calls
+ * is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ * 2. Operators
+ * ------------
+ * number approximate
+ * percentage
+ *
+ * Arithmetic 32 50.8
+ *
+ * + 21 33.3
+ * - 7 11.1
+ * * 3 4.8
+ * / (int div) 1 1.6
+ *
+ * Comparison 27 42.8
+ *
+ * == 9 14.3
+ * /= 4 6.3
+ * > 1 1.6
+ * < 3 4.8
+ * >= 1 1.6
+ * <= 9 14.3
+ *
+ * Logic 4 6.3
+ *
+ * && (AND-THEN) 1 1.6
+ * | (OR) 1 1.6
+ * ! (NOT) 2 3.2
+ *
+ * -- -----
+ * 63 100.1
+ *
+ *
+ * 3. Operand Type (counted once per operand reference):
+ * ---------------
+ * number approximate
+ * percentage
+ *
+ * Integer 175 72.3 %
+ * Character 45 18.6 %
+ * Pointer 12 5.0 %
+ * String30 6 2.5 %
+ * Array 2 0.8 %
+ * Record 2 0.8 %
+ * --- -------
+ * 242 100.0 %
+ *
+ * When there is an access path leading to the final operand (e.g. a record
+ * component), only the final data type on the access path is counted.
+ *
+ *
+ * 4. Operand Locality:
+ * -------------------
+ * number approximate
+ * percentage
+ *
+ * local variable 114 47.1 %
+ * global variable 22 9.1 %
+ * parameter 45 18.6 %
+ * value 23 9.5 %
+ * reference 22 9.1 %
+ * function result 6 2.5 %
+ * constant 55 22.7 %
+ * --- -------
+ * 242 100.0 %
+ *
+ *
+ * The program does not compute anything meaningful, but it is syntactically
+ * and semantically correct. All variables have a value assigned to them
+ * before they are used as a source operand.
+ *
+ * There has been no explicit effort to account for the effects of a
+ * cache, or to balance the use of long or short displacements for code or
+ * data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+#ifndef TIME
+#define TIMES
+#endif
+ /* Use times(2) time function unless */
+ /* explicitly defined otherwise */
+
+#ifdef TIMES
+#include <sys/types.h>
+#include <sys/times.h>
+ /* for "times" */
+#endif
+
+#define Mic_secs_Per_Second 1000000
+ /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef NOSTRUCTASSIGN
+#define structassign(d, s) memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s) d = s
+#endif
+
+#ifdef NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+ typedef int Enumeration;
+#else
+ typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+ Enumeration;
+#endif
+ /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+ /* for strcpy, strcmp */
+
+#define Null 0
+ /* Value of a Null pointer */
+#define true 1
+#define false 0
+
+typedef int One_Thirty;
+typedef int One_Fifty;
+typedef char Capital_Letter;
+typedef int Boolean;
+typedef char Str_30 [31];
+typedef int Arr_1_Dim [50];
+typedef int Arr_2_Dim [50] [50];
+
+typedef struct record
+ {
+ struct record *Ptr_Comp;
+ Enumeration Discr;
+ union {
+ struct {
+ Enumeration Enum_Comp;
+ int Int_Comp;
+ char Str_Comp [31];
+ } var_1;
+ struct {
+ Enumeration E_Comp_2;
+ char Str_2_Comp [31];
+ } var_2;
+ struct {
+ char Ch_1_Comp;
+ char Ch_2_Comp;
+ } var_3;
+ } variant;
+ } Rec_Type, *Rec_Pointer;
+
+
diff --git a/software/dhrystone/dhry_1.c b/software/dhrystone/dhry_1.c
new file mode 100644
index 0000000..7ab02a8
--- /dev/null
+++ b/software/dhrystone/dhry_1.c
@@ -0,0 +1,385 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_1.c (part 2 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+/* Global Variables: */
+
+Rec_Pointer Ptr_Glob,
+ Next_Ptr_Glob;
+int Int_Glob;
+Boolean Bool_Glob;
+char Ch_1_Glob,
+ Ch_2_Glob;
+int Arr_1_Glob [50];
+int Arr_2_Glob [50] [50];
+
+extern char *malloc ();
+Enumeration Func_1 ();
+ /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+ Boolean Reg = false;
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#else
+ Boolean Reg = true;
+#endif
+
+/* variables for time measurement: */
+
+#ifdef TIMES
+struct tms time_info;
+extern int times ();
+ /* see library function "times" */
+#define Too_Small_Time 120
+ /* Measurements should last at least about 2 seconds */
+#endif
+#ifdef TIME
+extern long time();
+ /* see library function "time" */
+#define Too_Small_Time 2
+ /* Measurements should last at least 2 seconds */
+#endif
+
+long Begin_Time,
+ End_Time,
+ User_Time;
+float Microseconds,
+ Dhrystones_Per_Second;
+
+/* end of variables for time measurement */
+
+
+main ()
+/*****/
+
+ /* main program, corresponds to procedures */
+ /* Main and Proc_0 in the Ada version */
+{
+ One_Fifty Int_1_Loc;
+ REG One_Fifty Int_2_Loc;
+ One_Fifty Int_3_Loc;
+ REG char Ch_Index;
+ Enumeration Enum_Loc;
+ Str_30 Str_1_Loc;
+ Str_30 Str_2_Loc;
+ REG int Run_Index;
+ REG int Number_Of_Runs;
+
+ /* Initializations */
+
+ Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+ Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+ Ptr_Glob->Ptr_Comp = Next_Ptr_Glob;
+ Ptr_Glob->Discr = Ident_1;
+ Ptr_Glob->variant.var_1.Enum_Comp = Ident_3;
+ Ptr_Glob->variant.var_1.Int_Comp = 40;
+ strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+ "DHRYSTONE PROGRAM, SOME STRING");
+ strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+ Arr_2_Glob [8][7] = 10;
+ /* Was missing in published program. Without this statement, */
+ /* Arr_2_Glob [8][7] would have an undefined value. */
+ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
+ /* overflow may occur for this array element. */
+
+ printf ("\n");
+ printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+ printf ("\n");
+ if (Reg)
+ {
+ printf ("Program compiled with 'register' attribute\n");
+ printf ("\n");
+ }
+ else
+ {
+ printf ("Program compiled without 'register' attribute\n");
+ printf ("\n");
+ }
+ printf ("Please give the number of runs through the benchmark: ");
+ {
+ int n;
+ scanf ("%d", &n);
+ Number_Of_Runs = n;
+ }
+ printf ("\n");
+
+ printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
+
+ /***************/
+ /* Start timer */
+ /***************/
+
+#ifdef TIMES
+ times (&time_info);
+ Begin_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ Begin_Time = time ( (long *) 0);
+#endif
+
+ for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+ {
+
+ Proc_5();
+ Proc_4();
+ /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+ Int_1_Loc = 2;
+ Int_2_Loc = 3;
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+ Enum_Loc = Ident_2;
+ Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+ /* Bool_Glob == 1 */
+ while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
+ {
+ Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+ /* Int_3_Loc == 7 */
+ Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+ /* Int_3_Loc == 7 */
+ Int_1_Loc += 1;
+ } /* while */
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+ /* Int_Glob == 5 */
+ Proc_1 (Ptr_Glob);
+ for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+ /* loop body executed twice */
+ {
+ if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+ /* then, not executed */
+ {
+ Proc_6 (Ident_1, &Enum_Loc);
+ strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+ Int_2_Loc = Run_Index;
+ Int_Glob = Run_Index;
+ }
+ }
+ /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+ Int_2_Loc = Int_2_Loc * Int_1_Loc;
+ Int_1_Loc = Int_2_Loc / Int_3_Loc;
+ Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+ /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+ Proc_2 (&Int_1_Loc);
+ /* Int_1_Loc == 5 */
+
+ } /* loop "for Run_Index" */
+
+ /**************/
+ /* Stop timer */
+ /**************/
+
+#ifdef TIMES
+ times (&time_info);
+ End_Time = (long) time_info.tms_utime;
+#endif
+#ifdef TIME
+ End_Time = time ( (long *) 0);
+#endif
+
+ printf ("Execution ends\n");
+ printf ("\n");
+ printf ("Final values of the variables used in the benchmark:\n");
+ printf ("\n");
+ printf ("Int_Glob: %d\n", Int_Glob);
+ printf (" should be: %d\n", 5);
+ printf ("Bool_Glob: %d\n", Bool_Glob);
+ printf (" should be: %d\n", 1);
+ printf ("Ch_1_Glob: %c\n", Ch_1_Glob);
+ printf (" should be: %c\n", 'A');
+ printf ("Ch_2_Glob: %c\n", Ch_2_Glob);
+ printf (" should be: %c\n", 'B');
+ printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]);
+ printf (" should be: %d\n", 7);
+ printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
+ printf (" should be: Number_Of_Runs + 10\n");
+ printf ("Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent)\n");
+ printf (" Discr: %d\n", Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 2);
+ printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 17);
+ printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Next_Ptr_Glob->\n");
+ printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+ printf (" should be: (implementation-dependent), same as above\n");
+ printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
+ printf (" should be: %d\n", 0);
+ printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+ printf (" should be: %d\n", 1);
+ printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+ printf (" should be: %d\n", 18);
+ printf (" Str_Comp: %s\n",
+ Next_Ptr_Glob->variant.var_1.Str_Comp);
+ printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
+ printf ("Int_1_Loc: %d\n", Int_1_Loc);
+ printf (" should be: %d\n", 5);
+ printf ("Int_2_Loc: %d\n", Int_2_Loc);
+ printf (" should be: %d\n", 13);
+ printf ("Int_3_Loc: %d\n", Int_3_Loc);
+ printf (" should be: %d\n", 7);
+ printf ("Enum_Loc: %d\n", Enum_Loc);
+ printf (" should be: %d\n", 1);
+ printf ("Str_1_Loc: %s\n", Str_1_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
+ printf ("Str_2_Loc: %s\n", Str_2_Loc);
+ printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
+ printf ("\n");
+
+ User_Time = End_Time - Begin_Time;
+
+ if (User_Time < Too_Small_Time)
+ {
+ printf ("Measured time too small to obtain meaningful results\n");
+ printf ("Please increase number of runs\n");
+ printf ("\n");
+ }
+ else
+ {
+#ifdef TIME
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / (float) Number_Of_Runs;
+ Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
+#else
+ Microseconds = (float) User_Time * Mic_secs_Per_Second
+ / ((float) HZ * ((float) Number_Of_Runs));
+ Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
+ / (float) User_Time;
+#endif
+ printf ("Microseconds for one run through Dhrystone: ");
+ printf ("%6.1f \n", Microseconds);
+ printf ("Dhrystones per Second: ");
+ printf ("%6.1f \n", Dhrystones_Per_Second);
+ printf ("\n");
+ }
+
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+ /* executed once */
+{
+ REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+ /* == Ptr_Glob_Next */
+ /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */
+ /* corresponds to "rename" in Ada, "with" in Pascal */
+
+ structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+ Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+ Next_Record->variant.var_1.Int_Comp
+ = Ptr_Val_Par->variant.var_1.Int_Comp;
+ Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+ Proc_3 (&Next_Record->Ptr_Comp);
+ /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
+ == Ptr_Glob->Ptr_Comp */
+ if (Next_Record->Discr == Ident_1)
+ /* then, executed */
+ {
+ Next_Record->variant.var_1.Int_Comp = 6;
+ Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
+ &Next_Record->variant.var_1.Enum_Comp);
+ Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+ Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+ &Next_Record->variant.var_1.Int_Comp);
+ }
+ else /* not executed */
+ structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+ /* executed once */
+ /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+ Enumeration Enum_Loc;
+
+ Int_Loc = *Int_Par_Ref + 10;
+ do /* executed once */
+ if (Ch_1_Glob == 'A')
+ /* then, executed */
+ {
+ Int_Loc -= 1;
+ *Int_Par_Ref = Int_Loc - Int_Glob;
+ Enum_Loc = Ident_1;
+ } /* if */
+ while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+ /* executed once */
+ /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+ if (Ptr_Glob != Null)
+ /* then, executed */
+ *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+ Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Boolean Bool_Loc;
+
+ Bool_Loc = Ch_1_Glob == 'A';
+ Bool_Glob = Bool_Loc | Bool_Glob;
+ Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+ /* executed once */
+{
+ Ch_1_Glob = 'A';
+ Bool_Glob = false;
+} /* Proc_5 */
+
+
+ /* Procedure for the assignment of structures, */
+ /* if the C compiler doesn't support this feature */
+#ifdef NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char *d;
+register char *s;
+register int l;
+{
+ while (l--) *d++ = *s++;
+}
+#endif
+
+
diff --git a/software/dhrystone/dhry_2.c b/software/dhrystone/dhry_2.c
new file mode 100644
index 0000000..63a3d3e
--- /dev/null
+++ b/software/dhrystone/dhry_2.c
@@ -0,0 +1,192 @@
+/*
+ ****************************************************************************
+ *
+ * "DHRYSTONE" Benchmark Program
+ * -----------------------------
+ *
+ * Version: C, Version 2.1
+ *
+ * File: dhry_2.c (part 3 of 3)
+ *
+ * Date: May 25, 1988
+ *
+ * Author: Reinhold P. Weicker
+ *
+ ****************************************************************************
+ */
+
+#include "dhry.h"
+
+#ifndef REG
+#define REG
+ /* REG becomes defined as empty */
+ /* i.e. no register variables */
+#endif
+
+extern int Int_Glob;
+extern char Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+ /* executed once */
+ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+ *Enum_Ref_Par = Enum_Val_Par;
+ if (! Func_3 (Enum_Val_Par))
+ /* then, not executed */
+ *Enum_Ref_Par = Ident_4;
+ switch (Enum_Val_Par)
+ {
+ case Ident_1:
+ *Enum_Ref_Par = Ident_1;
+ break;
+ case Ident_2:
+ if (Int_Glob > 100)
+ /* then */
+ *Enum_Ref_Par = Ident_1;
+ else *Enum_Ref_Par = Ident_4;
+ break;
+ case Ident_3: /* executed */
+ *Enum_Ref_Par = Ident_2;
+ break;
+ case Ident_4: break;
+ case Ident_5:
+ *Enum_Ref_Par = Ident_3;
+ break;
+ } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+ /* executed three times */
+ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */
+ /* Int_Par_Ref becomes 7 */
+ /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+ /* Int_Par_Ref becomes 17 */
+ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+ /* Int_Par_Ref becomes 18 */
+One_Fifty Int_1_Par_Val;
+One_Fifty Int_2_Par_Val;
+One_Fifty *Int_Par_Ref;
+{
+ One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 2;
+ *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+ /* executed once */
+ /* Int_Par_Val_1 == 3 */
+ /* Int_Par_Val_2 == 7 */
+Arr_1_Dim Arr_1_Par_Ref;
+Arr_2_Dim Arr_2_Par_Ref;
+int Int_1_Par_Val;
+int Int_2_Par_Val;
+{
+ REG One_Fifty Int_Index;
+ REG One_Fifty Int_Loc;
+
+ Int_Loc = Int_1_Par_Val + 5;
+ Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+ Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+ Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+ for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+ Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+ Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+ Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+ Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+ /* executed three times */
+ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */
+ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */
+ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */
+
+Capital_Letter Ch_1_Par_Val;
+Capital_Letter Ch_2_Par_Val;
+{
+ Capital_Letter Ch_1_Loc;
+ Capital_Letter Ch_2_Loc;
+
+ Ch_1_Loc = Ch_1_Par_Val;
+ Ch_2_Loc = Ch_1_Loc;
+ if (Ch_2_Loc != Ch_2_Par_Val)
+ /* then, executed */
+ return (Ident_1);
+ else /* not executed */
+ {
+ Ch_1_Glob = Ch_1_Loc;
+ return (Ident_2);
+ }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+ /* executed once */
+ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30 Str_1_Par_Ref;
+Str_30 Str_2_Par_Ref;
+{
+ REG One_Thirty Int_Loc;
+ Capital_Letter Ch_Loc;
+
+ Int_Loc = 2;
+ while (Int_Loc <= 2) /* loop body executed once */
+ if (Func_1 (Str_1_Par_Ref[Int_Loc],
+ Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+ /* then, executed */
+ {
+ Ch_Loc = 'A';
+ Int_Loc += 1;
+ } /* if, while */
+ if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+ /* then, not executed */
+ Int_Loc = 7;
+ if (Ch_Loc == 'R')
+ /* then, not executed */
+ return (true);
+ else /* executed */
+ {
+ if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+ /* then, not executed */
+ {
+ Int_Loc += 7;
+ Int_Glob = Int_Loc;
+ return (true);
+ }
+ else /* executed */
+ return (false);
+ } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+ /* executed once */
+ /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+ Enumeration Enum_Loc;
+
+ Enum_Loc = Enum_Par_Val;
+ if (Enum_Loc == Ident_3)
+ /* then, executed */
+ return (true);
+ else /* not executed */
+ return (false);
+} /* Func_3 */
+
diff --git a/software/dhrystone/dhry_printf.c b/software/dhrystone/dhry_printf.c
new file mode 100644
index 0000000..1fdaac4
--- /dev/null
+++ b/software/dhrystone/dhry_printf.c
@@ -0,0 +1,271 @@
+/* The functions in this file are only meant to support Dhrystone on an
+ * embedded RV32 system and are obviously incorrect in general. */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+
+#undef putchar
+int putchar(int ch)
+{
+ return write(1, &ch, 1) == 1 ? ch : -1;
+}
+
+static void sprintf_putch(int ch, void** data)
+{
+ char** pstr = (char**)data;
+ **pstr = ch;
+ (*pstr)++;
+}
+
+static unsigned long getuint(va_list *ap, int lflag)
+{
+ if (lflag)
+ return va_arg(*ap, unsigned long);
+ else
+ return va_arg(*ap, unsigned int);
+}
+
+static long getint(va_list *ap, int lflag)
+{
+ if (lflag)
+ return va_arg(*ap, long);
+ else
+ return va_arg(*ap, int);
+}
+
+static inline void printnum(void (*putch)(int, void**), void **putdat,
+ unsigned long num, unsigned base, int width, int padc)
+{
+ unsigned digs[sizeof(num)*8];
+ int pos = 0;
+
+ while (1)
+ {
+ digs[pos++] = num % base;
+ if (num < base)
+ break;
+ num /= base;
+ }
+
+ while (width-- > pos)
+ putch(padc, putdat);
+
+ while (pos-- > 0)
+ putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
+}
+
+static inline void print_double(void (*putch)(int, void**), void **putdat,
+ double num, int width, int prec)
+{
+ union {
+ double d;
+ uint64_t u;
+ } u;
+ u.d = num;
+
+ if (u.u & (1ULL << 63)) {
+ putch('-', putdat);
+ u.u &= ~(1ULL << 63);
+ }
+
+ for (int i = 0; i < prec; i++)
+ u.d *= 10;
+
+ char buf[32], *pbuf = buf;
+ printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0);
+ if (prec > 0) {
+ for (int i = 0; i < prec; i++) {
+ pbuf[-i] = pbuf[-i-1];
+ }
+ pbuf[-prec] = '.';
+ pbuf++;
+ }
+
+ for (char* p = buf; p < pbuf; p++)
+ putch(*p, putdat);
+}
+
+static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
+{
+ register const char* p;
+ const char* last_fmt;
+ register int ch, err;
+ unsigned long num;
+ int base, lflag, width, precision, altflag;
+ char padc;
+
+ while (1) {
+ while ((ch = *(unsigned char *) fmt) != '%') {
+ if (ch == '\0')
+ return;
+ fmt++;
+ putch(ch, putdat);
+ }
+ fmt++;
+
+ // Process a %-escape sequence
+ last_fmt = fmt;
+ padc = ' ';
+ width = -1;
+ precision = -1;
+ lflag = 0;
+ altflag = 0;
+ reswitch:
+ switch (ch = *(unsigned char *) fmt++) {
+
+ // flag to pad on the right
+ case '-':
+ padc = '-';
+ goto reswitch;
+
+ // flag to pad with 0's instead of spaces
+ case '0':
+ padc = '0';
+ goto reswitch;
+
+ // width field
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ for (precision = 0; ; ++fmt) {
+ precision = precision * 10 + ch - '0';
+ ch = *fmt;
+ if (ch < '0' || ch > '9')
+ break;
+ }
+ goto process_precision;
+
+ case '*':
+ precision = va_arg(ap, int);
+ goto process_precision;
+
+ case '.':
+ if (width < 0)
+ width = 0;
+ goto reswitch;
+
+ case '#':
+ altflag = 1;
+ goto reswitch;
+
+ process_precision:
+ if (width < 0)
+ width = precision, precision = -1;
+ goto reswitch;
+
+ // long flag
+ case 'l':
+ if (lflag)
+ goto bad;
+ goto reswitch;
+
+ // character
+ case 'c':
+ putch(va_arg(ap, int), putdat);
+ break;
+
+ // double
+ case 'f':
+ print_double(putch, putdat, va_arg(ap, double), width, precision);
+ break;
+
+ // string
+ case 's':
+ if ((p = va_arg(ap, char *)) == NULL)
+ p = "(null)";
+ if (width > 0 && padc != '-')
+ for (width -= strnlen(p, precision); width > 0; width--)
+ putch(padc, putdat);
+ for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
+ putch(ch, putdat);
+ p++;
+ }
+ for (; width > 0; width--)
+ putch(' ', putdat);
+ break;
+
+ // (signed) decimal
+ case 'd':
+ num = getint(&ap, lflag);
+ if ((long) num < 0) {
+ putch('-', putdat);
+ num = -(long) num;
+ }
+ base = 10;
+ goto signed_number;
+
+ // unsigned decimal
+ case 'u':
+ base = 10;
+ goto unsigned_number;
+
+ // (unsigned) octal
+ case 'o':
+ // should do something with padding so it's always 3 octits
+ base = 8;
+ goto unsigned_number;
+
+ // pointer
+ case 'p':
+ lflag = 1;
+ putch('0', putdat);
+ putch('x', putdat);
+ /* fall through to 'x' */
+
+ // (unsigned) hexadecimal
+ case 'x':
+ base = 16;
+ unsigned_number:
+ num = getuint(&ap, lflag);
+ signed_number:
+ printnum(putch, putdat, num, base, width, padc);
+ break;
+
+ // escaped '%' character
+ case '%':
+ putch(ch, putdat);
+ break;
+
+ // unrecognized escape sequence - just print it literally
+ default:
+ bad:
+ putch('%', putdat);
+ fmt = last_fmt;
+ break;
+ }
+ }
+}
+
+int printf(const char* fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+
+ vprintfmt((void*)putchar, 0, fmt, ap);
+
+ va_end(ap);
+ return 0; // incorrect return value, but who cares, anyway?
+}
+
+int sprintf(char* str, const char* fmt, ...)
+{
+ va_list ap;
+ char* str0 = str;
+ va_start(ap, fmt);
+
+ vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
+ *str = 0;
+
+ va_end(ap);
+ return str - str0;
+}
diff --git a/software/dhrystone/dhry_stubs.c b/software/dhrystone/dhry_stubs.c
new file mode 100644
index 0000000..d384bf1
--- /dev/null
+++ b/software/dhrystone/dhry_stubs.c
@@ -0,0 +1,31 @@
+#include "platform.h"
+
+/* The functions in this file are only meant to support Dhrystone on an
+ * embedded RV32 system and are obviously incorrect in general. */
+
+// return the cycle counter as though it were the current time
+long time(void)
+{
+ long t;
+ asm volatile ("csrr %0, mcycle" : "=r" (t));
+ return t / (get_cpu_freq() / 1000);
+}
+
+// set the number of dhrystone iterations
+void scanf(const char* fmt, int* n)
+{
+ *n = 1500000;
+}
+
+// simple memory allocator
+void* malloc(unsigned long sz)
+{
+ extern void* sbrk(long);
+ void* res = sbrk(sz);
+ if ((long)res == -1)
+ return 0;
+ return res;
+}
+
+// simple memory deallocator
+void free(void* ptr) {}
diff --git a/software/hello/Makefile b/software/hello/Makefile
new file mode 100644
index 0000000..c0c5c55
--- /dev/null
+++ b/software/hello/Makefile
@@ -0,0 +1,6 @@
+TARGET = hello
+C_SRCS += hello.c
+CFLAGS += -fno-builtin-printf
+
+BSP_BASE = ../../bsp
+include $(BSP_BASE)/env/common.mk
diff --git a/software/hello/hello.c b/software/hello/hello.c
new file mode 100644
index 0000000..85c5d87
--- /dev/null
+++ b/software/hello/hello.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+int main()
+{
+ printf("hello world!\n");
+
+ return 0;
+}
diff --git a/software/shared/Makefile.shared b/software/shared/Makefile.shared
deleted file mode 100644
index 70550a0..0000000
--- a/software/shared/Makefile.shared
+++ /dev/null
@@ -1,48 +0,0 @@
-# See LICENSE for license details.
-
-SHARED_DIR = $(SWDIR)/shared
-
-ASM_SRCS += $(SHARED_DIR)/entry.S
-
-C_SRCS += $(SHARED_DIR)/init.c
-C_SRCS += $(SHARED_DIR)/syscall.c
-C_SRCS += $(SHARED_DIR)/drivers_sifive/plic.c
-
-PLATFORM ?= freedom-e300
-LINKER_SCRIPT := $(SWDIR)/../riscv-tests/debug/targets/$(PLATFORM)/link.lds
-HEADERS += $(SHARED_DIR)/*.h
-
-C_SRCS += $(TARGET).c
-
-INCLUDES += -I .
-INCLUDES += -I $(SHARED_DIR)
-INCLUDES += -I $(SWDIR)/../riscv-tests/env
-INCLUDES += -I$(SHARED_DIR)/drivers_sifive/
-
-CC = $(SWDIR)/../toolchain/bin/riscv32-unknown-elf-gcc
-
-CFLAGS += $(CDEFINES)
-
-LDFLAGS := -T $(LINKER_SCRIPT) -nostdlib -nostartfiles -lc -lgcc
-LDFLAGS += -L$(SHARED_DIR)
-LDFLAGS += -L$(SHARED_DIR)/drivers
-LDFLAGS += -L$(SHARED_DIR)/hal
-
-ASM_OBJS := $(patsubst %.S,%.o,$(ASM_SRCS))
-C_OBJS := $(patsubst %.c,%.o,$(C_SRCS))
-
-$(TARGET): $(ASM_OBJS) $(C_OBJS) $(LINKER_SCRIPT)
- $(CC) $(CFLAGS) $(INCLUDES) $(C_OBJS) $(ASM_OBJS) -o $@ $(LDFLAGS)
-
-$(ASM_OBJS): %.o: %.S $(HEADERS)
- $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
-
-$(C_OBJS): %.o: %.c $(HEADERS)
- $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
-
-all: default
-
-clean:
- rm -f $(TARGET) *.o $(SHARED_DIR)/*.o $(SHARED_DIR)/drivers/*/*.o $(SHARED_DIR)/drivers_sifive/*.o
-
-.PHONY: clean all default
diff --git a/software/shared/drivers_sifive/plic.h b/software/shared/drivers_sifive/plic.h
deleted file mode 100644
index 14118a5..0000000
--- a/software/shared/drivers_sifive/plic.h
+++ /dev/null
@@ -1,70 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef PLIC_H
-#define PLIC_H
-
-#include <stdlib.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <unistd.h>
-
-
-#include "encoding.h"
-
-// 32 bits per source
-#define PLIC_PRIORITY_OFFSET 0x0000UL
-#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
-// 1 bit per source (1 address)
-#define PLIC_PENDING_OFFSET 0x1000UL
-#define PLIC_PENDING_SHIFT_PER_SOURCE 0
-
-//0x80 per target
-#define PLIC_ENABLE_OFFSET 0x2000UL
-#define PLIC_ENABLE_SHIFT_PER_TARGET 7
-
-
-#define PLIC_THRESHOLD_OFFSET 0x200000UL
-#define PLIC_CLAIM_OFFSET 0x200004UL
-#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
-#define PLIC_CLAIM_SHIFT_PER_TARGET 12
-
-#define PLIC_MAX_SOURCE 1023
-#define PLIC_SOURCE_MASK 0x3FF
-
-#define PLIC_MAX_TARGET 15871
-#define PLIC_TARGET_MASK 0x3FFF
-
-
-typedef struct __plic_instance_t
-{
- uintptr_t base_addr;
-
- uint32_t num_sources;
- uint32_t num_priorities;
-
-} plic_instance_t;
-
-typedef uint32_t plic_source;
-typedef uint32_t plic_priority;
-typedef uint32_t plic_threshold;
-
-void PLIC_init (
- plic_instance_t * this_plic,
- uintptr_t base_addr,
- uint32_t num_sources,
- uint32_t num_priorities
- );
-
-void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source);
-
-void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source);
-
-void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority);
-
-plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
-
-void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source);
-
-void PLIC_set_threshold(plic_instance_t * this_plic, plic_threshold threshold);
-
-#endif
diff --git a/software/shared/entry.S b/software/shared/entry.S
deleted file mode 120000
index 11f412b..0000000
--- a/software/shared/entry.S
+++ /dev/null
@@ -1 +0,0 @@
-../../riscv-tests/debug/programs/entry.S \ No newline at end of file
diff --git a/software/shared/gpio.h b/software/shared/gpio.h
deleted file mode 100644
index ed48255..0000000
--- a/software/shared/gpio.h
+++ /dev/null
@@ -1,10 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef SIFIVE_GPIO_H
-#define SIFIVE_GPIO_H
-
-#define GPIO_IN_OFFSET 0
-#define GPIO_OUT_OFFSET 0
-#define GPIO_TRI_OFFSET 4
-
-#endif
diff --git a/software/shared/init.c b/software/shared/init.c
deleted file mode 100644
index ab790b2..0000000
--- a/software/shared/init.c
+++ /dev/null
@@ -1,48 +0,0 @@
-// See LICENSE for license details.
-
-#include <stdlib.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <unistd.h>
-
-#include "encoding.h"
-#include "shared.h"
-
-int main(void);
-
-#ifdef USE_PLIC
-extern void handle_m_ext_interrupt();
-#endif
-
-
-#ifdef USE_M_TIME
-extern void handle_m_time_interrupt();
-#endif
-
-
-void _init(void)
-{
-
- exit(main());
-}
-
-uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
-{
- if (0){
-#ifdef USE_PLIC
- // External Machine-Level Interrupt from PLIC
- }else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
- handle_m_ext_interrupt();
-#endif
-#ifdef USE_M_TIME
- // External Machine-Level Interrupt from PLIC
- }else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) {
- handle_m_time_interrupt();
-#endif
- }
- else{
- write(1, "trap\n", 5);
- _exit(1 + mcause);
- }
- return epc;
-}
diff --git a/software/shared/shared.h b/software/shared/shared.h
deleted file mode 100644
index e8f3bf4..0000000
--- a/software/shared/shared.h
+++ /dev/null
@@ -1,73 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef SIFIVE_SHARED_H
-#define SIFIVE_SHARED_H
-
-#include "uart.h"
-#include "gpio.h"
-#include "plic.h"
-
-// Some things missing from the official encoding.h
-#define MCAUSE_INT 0x80000000
-#define MCAUSE_CAUSE 0x7FFFFFFF
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-#define MTIMECMP_BASE_ADDR 0x44004000UL
-#define MTIME_ADDR 0x4400BFF8UL
-#define PLIC_BASE_ADDR 0x40000000UL
-#define UART_BASE_ADDR 0x48000000UL
-#define GPIO_BASE_ADDR 0x48002000UL
-#define SPI_BASE_ADDR 0x48001000UL
-
-
-/****************************************************************************
- * Clock Parameters
- *****************************************************************************/
-
-#define RTC_PRESCALER 100
-#define CLOCK_FREQUENCY 62500000
-
-/****************************************************************************
- * GPIO Connections
- *****************************************************************************/
-
-
-// Each of these OFFSETS holds 4 bits.
-
-#define RED_LEDS_OFFSET 0
-#define GREEN_LEDS_OFFSET 4
-#define BLUE_LEDS_OFFSET 8
-#define JA_OUT_OFFSET 12 // JA Pins 1-4 are outputs.
-
-#define BUTTONS_OFFSET 16
-#define SWITCHES_OFFSET 20
-#define JA_IN_OFFSET 24 // JA Pins 7-10 are inputs.
-// reserved input offset 38 // Tied to zero.
-
-/****************************************************************************
- * External Interrupts handled by PLIC.
- *****************************************************************************/
-
-// Interrupt devices
-#define INT_DEVICE_BUTTON_0 1
-#define INT_DEVICE_BUTTON_1 2
-#define INT_DEVICE_BUTTON_2 3
-#define INT_DEVICE_BUTTON_3 4
-
-#define INT_DEVICE_JA_7 5
-#define INT_DEVICE_JA_8 6
-#define INT_DEVICE_JA_9 7
-#define INT_DEVICE_JA_10 8
-
-
-// Setting these correctly makes the initialization scripts
-// run faster.
-#define PLIC_NUM_SOURCES 31
-#define PLIC_NUM_PRIORITIES 0
-
-void write_hex(int fd, uint32_t hex);
-
-#endif
diff --git a/software/shared/spi.h b/software/shared/spi.h
deleted file mode 100644
index 9c974c1..0000000
--- a/software/shared/spi.h
+++ /dev/null
@@ -1,8 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef SIFIVE_SPI_H
-#define SIFIVE_SPI_H
-
-//TODO
-
-#endif
diff --git a/software/shared/uart.h b/software/shared/uart.h
deleted file mode 100644
index e97ef8b..0000000
--- a/software/shared/uart.h
+++ /dev/null
@@ -1,12 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef SIFIVE_UART_H
-#define SIFIVE_UART_H
-
-#define UART_RX_OFFSET 0
-#define UART_TX_OFFSET 0
-#define UART_TX_COUNT_OFFSET 0x4
-#define UART_RX_COUNT_OFFSET 0x8
-#define UART_DIVIDER_OFFSET 0xC
-
-#endif
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