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-rw-r--r--bsp/coreip-e21-arty/design.dts5
-rw-r--r--bsp/coreip-e21-rtl/design.dts5
-rw-r--r--bsp/coreip-e24-arty/design.dts5
-rw-r--r--bsp/coreip-e24-rtl/design.dts5
-rw-r--r--bsp/coreip-e31-arty/design.dts5
-rw-r--r--bsp/coreip-e31-rtl/design.dts5
-rw-r--r--bsp/coreip-e34-arty/design.dts5
-rw-r--r--bsp/coreip-e34-rtl/design.dts5
-rw-r--r--bsp/coreip-e76-arty/design.dts5
-rw-r--r--bsp/coreip-e76-rtl/design.dts5
-rw-r--r--bsp/coreip-s51-arty/design.dts5
-rw-r--r--bsp/coreip-s51-rtl/design.dts5
-rw-r--r--bsp/coreip-s54-arty/design.dts5
-rw-r--r--bsp/coreip-s54-rtl/design.dts5
-rw-r--r--bsp/coreip-s76-arty/design.dts5
-rw-r--r--bsp/coreip-s76-rtl/design.dts5
-rw-r--r--bsp/coreip-u54-rtl/design.dts5
-rw-r--r--bsp/coreip-u54mc-rtl/design.dts9
-rw-r--r--bsp/sifive-hifive-unleashed/design.dts9
-rw-r--r--bsp/sifive-hifive1-revb/design.dts7
20 files changed, 28 insertions, 82 deletions
diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts
index 7303568..40f61d0 100644
--- a/bsp/coreip-e21-arty/design.dts
+++ b/bsp/coreip-e21-arty/design.dts
@@ -21,6 +21,7 @@
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <4>;
status = "okay";
timebase-frequency = <32000000>;
hardware-exec-breakpoint-count = <4>;
@@ -36,10 +37,6 @@
#size-cells = <1>;
compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <4>;
- };
hfclk: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/bsp/coreip-e21-rtl/design.dts b/bsp/coreip-e21-rtl/design.dts
index 9e846c0..ed9fa86 100644
--- a/bsp/coreip-e21-rtl/design.dts
+++ b/bsp/coreip-e21-rtl/design.dts
@@ -14,6 +14,7 @@
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <4>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
@@ -29,10 +30,6 @@
#size-cells = <1>;
compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L11: ahb-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts
index f288b54..ba6b037 100644
--- a/bsp/coreip-e24-arty/design.dts
+++ b/bsp/coreip-e24-arty/design.dts
@@ -21,6 +21,7 @@
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <4>;
status = "okay";
timebase-frequency = <32000000>;
hardware-exec-breakpoint-count = <4>;
@@ -36,10 +37,6 @@
#size-cells = <1>;
compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <4>;
- };
hfclk: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/bsp/coreip-e24-rtl/design.dts b/bsp/coreip-e24-rtl/design.dts
index da1b792..a254a10 100644
--- a/bsp/coreip-e24-rtl/design.dts
+++ b/bsp/coreip-e24-rtl/design.dts
@@ -14,6 +14,7 @@
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <4>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
@@ -29,10 +30,6 @@
#size-cells = <1>;
compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L11: ahb-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts
index e9dda78..cf5dcab 100644
--- a/bsp/coreip-e31-arty/design.dts
+++ b/bsp/coreip-e31-arty/design.dts
@@ -25,6 +25,7 @@
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -47,10 +48,6 @@
compatible = "fixed-clock";
clock-frequency = <32500000>;
};
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-e31-rtl/design.dts b/bsp/coreip-e31-rtl/design.dts
index 7c527ec..6bfbf1a 100644
--- a/bsp/coreip-e31-rtl/design.dts
+++ b/bsp/coreip-e31-rtl/design.dts
@@ -17,6 +17,7 @@
i-cache-size = <16384>;
reg = <0x0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -34,10 +35,6 @@
#size-cells = <1>;
compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L12: ahb-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/bsp/coreip-e34-arty/design.dts b/bsp/coreip-e34-arty/design.dts
index d0e640b..4cb0962 100644
--- a/bsp/coreip-e34-arty/design.dts
+++ b/bsp/coreip-e34-arty/design.dts
@@ -25,6 +25,7 @@
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -47,10 +48,6 @@
compatible = "fixed-clock";
clock-frequency = <32500000>;
};
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-e34-rtl/design.dts b/bsp/coreip-e34-rtl/design.dts
index 142e9d4..745f2b4 100644
--- a/bsp/coreip-e34-rtl/design.dts
+++ b/bsp/coreip-e34-rtl/design.dts
@@ -17,6 +17,7 @@
i-cache-size = <16384>;
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -34,10 +35,6 @@
#size-cells = <1>;
compatible = "SiFive,FE340G-soc", "fe340-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L12: ahb-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/bsp/coreip-e76-arty/design.dts b/bsp/coreip-e76-arty/design.dts
index 1ea526f..c1ef3b2 100644
--- a/bsp/coreip-e76-arty/design.dts
+++ b/bsp/coreip-e76-arty/design.dts
@@ -28,6 +28,7 @@
next-level-cache = <&L14 &L15>;
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <65000000>;
hardware-exec-breakpoint-count = <4>;
@@ -47,10 +48,6 @@
#size-cells = <1>;
compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-e76-rtl/design.dts b/bsp/coreip-e76-rtl/design.dts
index 40c0004..25bd59c 100644
--- a/bsp/coreip-e76-rtl/design.dts
+++ b/bsp/coreip-e76-rtl/design.dts
@@ -21,6 +21,7 @@
next-level-cache = <&L9>;
reg = <0x0>;
riscv,isa = "rv32imafc";
+ riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
@@ -40,10 +41,6 @@
#size-cells = <1>;
compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L11: axi4-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts
index 7d8e0d2..3bcab05 100644
--- a/bsp/coreip-s51-arty/design.dts
+++ b/bsp/coreip-s51-arty/design.dts
@@ -25,6 +25,7 @@
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv64imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -47,10 +48,6 @@
compatible = "fixed-clock";
clock-frequency = <32500000>;
};
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-s51-rtl/design.dts b/bsp/coreip-s51-rtl/design.dts
index bbbab4d..3a7bf54 100644
--- a/bsp/coreip-s51-rtl/design.dts
+++ b/bsp/coreip-s51-rtl/design.dts
@@ -17,6 +17,7 @@
i-cache-size = <16384>;
reg = <0x0>;
riscv,isa = "rv64imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -34,10 +35,6 @@
#size-cells = <2>;
compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L12: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/bsp/coreip-s54-arty/design.dts b/bsp/coreip-s54-arty/design.dts
index ae42f18..1ae14e2 100644
--- a/bsp/coreip-s54-arty/design.dts
+++ b/bsp/coreip-s54-arty/design.dts
@@ -25,6 +25,7 @@
next-level-cache = <&L10>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -47,10 +48,6 @@
compatible = "fixed-clock";
clock-frequency = <32500000>;
};
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-s54-rtl/design.dts b/bsp/coreip-s54-rtl/design.dts
index f5a21b4..118fe04 100644
--- a/bsp/coreip-s54-rtl/design.dts
+++ b/bsp/coreip-s54-rtl/design.dts
@@ -17,6 +17,7 @@
i-cache-size = <16384>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L6>;
sifive,itim = <&L5>;
status = "okay";
@@ -34,10 +35,6 @@
#size-cells = <2>;
compatible = "SiFive,FS540G-soc", "fs540-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L12: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/bsp/coreip-s76-arty/design.dts b/bsp/coreip-s76-arty/design.dts
index b5af1f3..00ed9ee 100644
--- a/bsp/coreip-s76-arty/design.dts
+++ b/bsp/coreip-s76-arty/design.dts
@@ -28,6 +28,7 @@
next-level-cache = <&L14 &L15>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <65000000>;
hardware-exec-breakpoint-count = <4>;
@@ -47,10 +48,6 @@
#size-cells = <1>;
compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <1>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-s76-rtl/design.dts b/bsp/coreip-s76-rtl/design.dts
index a4fd9c8..690b6a4 100644
--- a/bsp/coreip-s76-rtl/design.dts
+++ b/bsp/coreip-s76-rtl/design.dts
@@ -21,6 +21,7 @@
next-level-cache = <&L9>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
@@ -40,10 +41,6 @@
#size-cells = <2>;
compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L11: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/bsp/coreip-u54-rtl/design.dts b/bsp/coreip-u54-rtl/design.dts
index b773072..154dc42 100644
--- a/bsp/coreip-u54-rtl/design.dts
+++ b/bsp/coreip-u54-rtl/design.dts
@@ -26,6 +26,7 @@
next-level-cache = <&L16>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L6>;
status = "okay";
timebase-frequency = <1000000>;
@@ -46,10 +47,6 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L13: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts
index 27a3c94..beba177 100644
--- a/bsp/coreip-u54mc-rtl/design.dts
+++ b/bsp/coreip-u54mc-rtl/design.dts
@@ -18,6 +18,7 @@
next-level-cache = <&L33>;
reg = <0x0>;
riscv,isa = "rv64imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L7>;
sifive,itim = <&L6>;
status = "okay";
@@ -46,6 +47,7 @@
next-level-cache = <&L33>;
reg = <0x1>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L11>;
status = "okay";
timebase-frequency = <1000000>;
@@ -74,6 +76,7 @@
next-level-cache = <&L33>;
reg = <0x2>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L15>;
status = "okay";
timebase-frequency = <1000000>;
@@ -102,6 +105,7 @@
next-level-cache = <&L33>;
reg = <0x3>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L19>;
status = "okay";
timebase-frequency = <1000000>;
@@ -130,6 +134,7 @@
next-level-cache = <&L33>;
reg = <0x4>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L23>;
status = "okay";
timebase-frequency = <1000000>;
@@ -150,10 +155,6 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
L30: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts
index ee6897f..8702be3 100644
--- a/bsp/sifive-hifive-unleashed/design.dts
+++ b/bsp/sifive-hifive-unleashed/design.dts
@@ -33,6 +33,7 @@
next-level-cache = <&L24 &L0>;
reg = <0>;
riscv,isa = "rv64imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L8>;
sifive,itim = <&L7>;
status = "okay";
@@ -60,6 +61,7 @@
next-level-cache = <&L24 &L0>;
reg = <1>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L11>;
status = "okay";
tlb-split;
@@ -87,6 +89,7 @@
next-level-cache = <&L24 &L0>;
reg = <2>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L14>;
status = "okay";
tlb-split;
@@ -114,6 +117,7 @@
next-level-cache = <&L24 &L0>;
reg = <3>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L17>;
status = "okay";
tlb-split;
@@ -141,6 +145,7 @@
next-level-cache = <&L24 &L0>;
reg = <4>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L20>;
status = "okay";
tlb-split;
@@ -160,10 +165,6 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <1>;
- };
refclk: refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts
index 0e48622..970d3be 100644
--- a/bsp/sifive-hifive1-revb/design.dts
+++ b/bsp/sifive-hifive1-revb/design.dts
@@ -25,6 +25,7 @@
next-level-cache = <&spi0>;
reg = <0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&dtim>;
status = "okay";
timebase-frequency = <1000000>;
@@ -43,12 +44,6 @@
#clock-cells = <1>;
compatible = "sifive,hifive1";
ranges;
-
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
-
hfxoscin: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 10:18:17 +0000