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-rw-r--r--FreedomStudio/E2FPGA/clic_vectored/.cproject208
-rw-r--r--FreedomStudio/E2FPGA/clic_vectored/.gitignore1
-rw-r--r--FreedomStudio/E2FPGA/clic_vectored/.project358
-rw-r--r--FreedomStudio/E2FPGA/clic_vectored/clic_vectored OpenOCD.launch61
-rw-r--r--FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg31
-rw-r--r--FreedomStudio/E2FPGA/coreplexip_welcome/.cproject210
-rw-r--r--FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore1
-rw-r--r--FreedomStudio/E2FPGA/coreplexip_welcome/.project358
-rw-r--r--FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch61
-rw-r--r--FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg31
-rw-r--r--FreedomStudio/E2FPGA/dhrystone/.cproject216
-rw-r--r--FreedomStudio/E2FPGA/dhrystone/.gitignore1
-rw-r--r--FreedomStudio/E2FPGA/dhrystone/.project373
-rw-r--r--FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch61
-rw-r--r--FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/.cproject210
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/.project363
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch63
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.cproject216
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.project383
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml25
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch62
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/.cproject215
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/.project363
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOCD.launch62
-rw-r--r--FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/.cproject210
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/.project363
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch62
-rw-r--r--FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/.cproject200
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/.project363
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/performance_counters OpenOCD.launch60
-rw-r--r--FreedomStudio/E31FPGA/performance_counters/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/.cproject211
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/.project358
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg31
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch61
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/.cproject210
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/.project353
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch61
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.cproject213
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.project378
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml25
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch62
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/.cproject210
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/.project353
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch60
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/.cproject210
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/.project353
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch60
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/.cproject208
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/.project353
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch60
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/.cproject211
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/.gitignore1
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/.project353
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch60
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/.cproject211
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/.gitignore1
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/.project348
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch61
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json2325
-rw-r--r--FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg34
-rw-r--r--FreedomStudio/HiFive1/dhrystone/.cproject211
-rw-r--r--FreedomStudio/HiFive1/dhrystone/.gitignore1
-rw-r--r--FreedomStudio/HiFive1/dhrystone/.project368
-rw-r--r--FreedomStudio/HiFive1/dhrystone/dhrystone.launch61
-rw-r--r--FreedomStudio/HiFive1/dhrystone/fe310-xsvd.json2325
-rw-r--r--FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg34
-rw-r--r--FreedomStudio/HiFive1/hello/.cproject208
-rw-r--r--FreedomStudio/HiFive1/hello/.gitignore1
-rw-r--r--FreedomStudio/HiFive1/hello/.project348
-rw-r--r--FreedomStudio/HiFive1/hello/fe310-xsvd.json2325
-rw-r--r--FreedomStudio/HiFive1/hello/hello OpenOCD.launch60
-rw-r--r--FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg34
-rw-r--r--FreedomStudio/HiFive1/led_fade/.cproject210
-rw-r--r--FreedomStudio/HiFive1/led_fade/.gitignore1
-rw-r--r--FreedomStudio/HiFive1/led_fade/.project348
-rw-r--r--FreedomStudio/HiFive1/led_fade/fe310-xsvd.json2325
-rw-r--r--FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch60
-rw-r--r--FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg34
119 files changed, 0 insertions, 37323 deletions
diff --git a/FreedomStudio/E2FPGA/clic_vectored/.cproject b/FreedomStudio/E2FPGA/clic_vectored/.cproject
deleted file mode 100644
index 85a0e97..0000000
--- a/FreedomStudio/E2FPGA/clic_vectored/.cproject
+++ /dev/null
@@ -1,208 +0,0 @@
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- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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diff --git a/FreedomStudio/E2FPGA/clic_vectored/.gitignore b/FreedomStudio/E2FPGA/clic_vectored/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E2FPGA/clic_vectored/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E2FPGA/clic_vectored/.project b/FreedomStudio/E2FPGA/clic_vectored/.project
deleted file mode 100644
index 9f821d4..0000000
--- a/FreedomStudio/E2FPGA/clic_vectored/.project
+++ /dev/null
@@ -1,358 +0,0 @@
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- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-arty.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
- </link>
- <link>
- <name>bsp/env/entry.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
- </link>
- <link>
- <name>bsp/env/hifive1.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
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- <link>
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- <type>1</type>
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- </link>
- <link>
- <name>bsp/include/sifive</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
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- <link>
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- <type>2</type>
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- <link>
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- <locationURI>virtual:/virtual</locationURI>
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- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/clic/clic_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/settings.mk</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/tim-split.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/tim.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
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- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
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- <link>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E2FPGA/clic_vectored/clic_vectored OpenOCD.launch b/FreedomStudio/E2FPGA/clic_vectored/clic_vectored OpenOCD.launch
deleted file mode 100644
index f900b1b..0000000
--- a/FreedomStudio/E2FPGA/clic_vectored/clic_vectored OpenOCD.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreip-e2-arty.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
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diff --git a/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject
deleted file mode 100644
index 051c949..0000000
--- a/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
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-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
- <folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722." name="/" resourcePath="">
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diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore b/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.project b/FreedomStudio/E2FPGA/coreplexip_welcome/.project
deleted file mode 100644
index 29e06f6..0000000
--- a/FreedomStudio/E2FPGA/coreplexip_welcome/.project
+++ /dev/null
@@ -1,358 +0,0 @@
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- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
deleted file mode 100644
index 356c25a..0000000
--- a/FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreip-e2-arty.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/coreplexip_welcome"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E2FPGA/dhrystone/.cproject b/FreedomStudio/E2FPGA/dhrystone/.cproject
deleted file mode 100644
index 863a5a9..0000000
--- a/FreedomStudio/E2FPGA/dhrystone/.cproject
+++ /dev/null
@@ -1,216 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
- <folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722." name="/" resourcePath="">
- <toolChain errorParsers="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug.1407212463" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug">
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting.1304654652" name="Create extended listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createlisting" useByScannerDiscovery="false"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize.952377303" name="Print size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1145706094" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.most" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.120899886" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.1496840810" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections.1808248879" name="Function sections (-ffunction-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections.1701706933" name="Data sections (-fdata-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.745111521" name="Debug level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.max" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format.1611143071" name="Debug format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format" useByScannerDiscovery="true"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp.388455619" name="C++ compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy.883015188" name="Hex/Bin converter" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1788482879" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv32i" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.427474672" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin.120978954" name="Disable builtin (-fno-builtin)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
- <builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" errorParsers="org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.CWDLocator" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
- <tool command="${cross_prefix}${cross_c}${cross_suffix}" commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1772574500" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1451354185" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.2050116277" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../../../../bsp/include"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env/coreip-e2-arty"/>
- <listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- </option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
- <inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
- </tool>
- <tool command="${cross_prefix}${cross_c}${cross_suffix}" commandLinePattern="${COMMAND} ${cross_toolchain_flags} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" errorParsers="org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.424460842" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
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- <listOptionValue builtIn="false" value="TIME"/>
- <listOptionValue builtIn="false" value="NOENUM"/>
- </option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../../../../bsp/include"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env/coreip-e2-arty"/>
- <listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- </option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.other.2042911660" name="Other compiler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.other" useByScannerDiscovery="true" value="-include sys/cdefs.h -c -fno-inline -fno-builtin-printf -Wno-implicit -fno-common -mexplicit-relocs -falign-functions=4" valueType="string"/>
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diff --git a/FreedomStudio/E2FPGA/dhrystone/.gitignore b/FreedomStudio/E2FPGA/dhrystone/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E2FPGA/dhrystone/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/FreedomStudio/E2FPGA/dhrystone/.project b/FreedomStudio/E2FPGA/dhrystone/.project
deleted file mode 100644
index 9776e74..0000000
--- a/FreedomStudio/E2FPGA/dhrystone/.project
+++ /dev/null
@@ -1,373 +0,0 @@
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- <name>bsp</name>
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- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>dhry.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry.h</locationURI>
- </link>
- <link>
- <name>dhry_1.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_1.c</locationURI>
- </link>
- <link>
- <name>dhry_2.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_2.c</locationURI>
- </link>
- <link>
- <name>dhry_printf.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_printf.c</locationURI>
- </link>
- <link>
- <name>dhry_stubs.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_stubs.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-arty.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
- </link>
- <link>
- <name>bsp/env/entry.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
- </link>
- <link>
- <name>bsp/env/hifive1.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
- </link>
- <link>
- <name>bsp/env/start.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/settings.mk</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/tim-split.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreip-e2-arty/tim.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch
deleted file mode 100644
index f996fc4..0000000
--- a/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreip-e2-arty.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/dhrystone.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dhrystone"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/dhrystone"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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diff --git a/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E31FPGA/coreplexip_welcome/.cproject
deleted file mode 100644
index 906fba6..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/.gitignore b/FreedomStudio/E31FPGA/coreplexip_welcome/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/.project b/FreedomStudio/E31FPGA/coreplexip_welcome/.project
deleted file mode 100644
index dcfbea2..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/.project
+++ /dev/null
@@ -1,363 +0,0 @@
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- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch
deleted file mode 100644
index dad28c2..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch
+++ /dev/null
@@ -1,80 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
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-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
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-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="4000"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/coreplexip_welcome"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
deleted file mode 100644
index b416a5c..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
+++ /dev/null
@@ -1,63 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals/&gt;&#10;"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e31-arty.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
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-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
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-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
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-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json b/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/dhrystone/.cproject b/FreedomStudio/E31FPGA/dhrystone/.cproject
deleted file mode 100644
index dba647c..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/.cproject
+++ /dev/null
@@ -1,216 +0,0 @@
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diff --git a/FreedomStudio/E31FPGA/dhrystone/.gitignore b/FreedomStudio/E31FPGA/dhrystone/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/dhrystone/.project b/FreedomStudio/E31FPGA/dhrystone/.project
deleted file mode 100644
index d5b2c53..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/.project
+++ /dev/null
@@ -1,383 +0,0 @@
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- <comment></comment>
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diff --git a/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml b/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml
deleted file mode 100644
index fa2c25a..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml
+++ /dev/null
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diff --git a/FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch b/FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch
deleted file mode 100644
index c331740..0000000
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diff --git a/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch
deleted file mode 100644
index f4ae61d..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch
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diff --git a/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json b/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/global_interrupts/.cproject b/FreedomStudio/E31FPGA/global_interrupts/.cproject
deleted file mode 100644
index 3d95eb4..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/.cproject
+++ /dev/null
@@ -1,215 +0,0 @@
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- <extensions>
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- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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- </tool>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1315189209" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1728208687" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format"/>
- </tool>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="coreplexip_welcome.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.84799689" name="Executable" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
- </storageModule>
- <storageModule moduleId="scannerConfiguration">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.743554394;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2132640858">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.424460842;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1695943366">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- </scannerConfigBuildInfo>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
- </configuration>
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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diff --git a/FreedomStudio/E31FPGA/global_interrupts/.gitignore b/FreedomStudio/E31FPGA/global_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/global_interrupts/.project b/FreedomStudio/E31FPGA/global_interrupts/.project
deleted file mode 100644
index 6745f61..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/.project
+++ /dev/null
@@ -1,363 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>global_interrupts</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <linkedResources>
- <link>
- <name>bsp</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>global_interrupts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/global_interrupts/global_interrupts.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-arty.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
- </link>
- <link>
- <name>bsp/env/entry.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
- </link>
- <link>
- <name>bsp/env/hifive1.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
- </link>
- <link>
- <name>bsp/env/start.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/dhrystone.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/dhrystone.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/scratchpad.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/scratchpad.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e31-arty/settings.mk</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/settings.mk</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch
deleted file mode 100644
index fbeda90..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch
+++ /dev/null
@@ -1,80 +0,0 @@
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
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-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
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-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/global_interrupts.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="global_interrupts"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
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-<listEntry value="/global_interrupts"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOCD.launch b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOCD.launch
deleted file mode 100644
index 6f43500..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOCD.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
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diff --git a/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/global_interrupts/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/local_interrupts/.cproject b/FreedomStudio/E31FPGA/local_interrupts/.cproject
deleted file mode 100644
index 3842f21..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
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- <externalSettings/>
- <extensions>
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- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
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- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
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diff --git a/FreedomStudio/E31FPGA/local_interrupts/.gitignore b/FreedomStudio/E31FPGA/local_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/local_interrupts/.project b/FreedomStudio/E31FPGA/local_interrupts/.project
deleted file mode 100644
index 43eecc9..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/.project
+++ /dev/null
@@ -1,363 +0,0 @@
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- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch
deleted file mode 100644
index 7ea0908..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch
+++ /dev/null
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diff --git a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch
deleted file mode 100644
index 35d484b..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch
+++ /dev/null
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-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/local_interrupts"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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diff --git a/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/local_interrupts/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/performance_counters/.cproject b/FreedomStudio/E31FPGA/performance_counters/.cproject
deleted file mode 100644
index 59b8831..0000000
--- a/FreedomStudio/E31FPGA/performance_counters/.cproject
+++ /dev/null
@@ -1,200 +0,0 @@
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- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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diff --git a/FreedomStudio/E31FPGA/performance_counters/.gitignore b/FreedomStudio/E31FPGA/performance_counters/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/performance_counters/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/performance_counters/.project b/FreedomStudio/E31FPGA/performance_counters/.project
deleted file mode 100644
index 0a7b057..0000000
--- a/FreedomStudio/E31FPGA/performance_counters/.project
+++ /dev/null
@@ -1,363 +0,0 @@
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- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json b/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch b/FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch
deleted file mode 100644
index d3f38d9..0000000
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diff --git a/FreedomStudio/E31FPGA/performance_counters/performance_counters OpenOCD.launch b/FreedomStudio/E31FPGA/performance_counters/performance_counters OpenOCD.launch
deleted file mode 100644
index 8b9c5cb..0000000
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diff --git a/FreedomStudio/E31FPGA/performance_counters/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/performance_counters/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/performance_counters/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.cproject b/FreedomStudio/E31FPGA/vectored_interrupts/.cproject
deleted file mode 100644
index f50ea8e..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/.cproject
+++ /dev/null
@@ -1,211 +0,0 @@
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- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
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- <listOptionValue builtIn="false" value="../../../../bsp/env"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e31-arty"/>
- <listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
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diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore b/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.project b/FreedomStudio/E31FPGA/vectored_interrupts/.project
deleted file mode 100644
index 94e835c..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/.project
+++ /dev/null
@@ -1,358 +0,0 @@
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diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json
deleted file mode 100644
index 4879d45..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json
+++ /dev/null
@@ -1,1250 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e31arty": {
- "displayName": "Core Complex E31 Arty",
- "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
- "headerTypePrefix": "sifive_e31arty_",
- "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "8",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "8",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch
deleted file mode 100644
index 0723d26..0000000
--- a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch
+++ /dev/null
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deleted file mode 100644
index 0574e02..0000000
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diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
deleted file mode 100644
index 7da94d5..0000000
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diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.gitignore b/FreedomStudio/E51FPGA/coreplexip_welcome/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.project b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
deleted file mode 100644
index e2d1392..0000000
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.project
+++ /dev/null
@@ -1,353 +0,0 @@
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- <locationURI>virtual:/virtual</locationURI>
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- <link>
- <name>bsp/env/coreplexip-arty.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
- </link>
- <link>
- <name>bsp/env/entry.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
- </link>
- <link>
- <name>bsp/env/hifive1.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
- </link>
- <link>
- <name>bsp/env/start.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/scratchpad.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/scratchpad.lds</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
deleted file mode 100644
index 9d170a8..0000000
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals&gt;&#10;&lt;peripheral name=&quot;gpio&quot;/&gt;&#10;&lt;/peripherals&gt;&#10;"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv64&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/coreplexip_welcome"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/dhrystone/.cproject b/FreedomStudio/E51FPGA/dhrystone/.cproject
deleted file mode 100644
index f27d03f..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/.cproject
+++ /dev/null
@@ -1,213 +0,0 @@
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diff --git a/FreedomStudio/E51FPGA/dhrystone/.gitignore b/FreedomStudio/E51FPGA/dhrystone/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/dhrystone/.project b/FreedomStudio/E51FPGA/dhrystone/.project
deleted file mode 100644
index 3683b2b..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/.project
+++ /dev/null
@@ -1,378 +0,0 @@
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- <comment></comment>
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- <name>bsp/env/coreplexip-e51-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/scratchpad.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/scratchpad.lds</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml b/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml
deleted file mode 100644
index d44fee0..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml
+++ /dev/null
@@ -1,25 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
- <configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug">
- <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
- <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
- <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-127277270154718449" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
- <language-scope id="org.eclipse.cdt.core.gcc"/>
- <language-scope id="org.eclipse.cdt.core.g++"/>
- </provider>
- </extension>
- </configuration>
- <configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491" name="Release">
- <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
- <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
- <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-216478794982700293" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
- <language-scope id="org.eclipse.cdt.core.gcc"/>
- <language-scope id="org.eclipse.cdt.core.g++"/>
- </provider>
- </extension>
- </configuration>
-</project>
diff --git a/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch
deleted file mode 100644
index 199c9c6..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv64&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/dhrystone.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dhrystone"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/dhrystone"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json b/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/global_interrupts/.cproject b/FreedomStudio/E51FPGA/global_interrupts/.cproject
deleted file mode 100644
index 672c12d..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
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diff --git a/FreedomStudio/E51FPGA/global_interrupts/.gitignore b/FreedomStudio/E51FPGA/global_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/global_interrupts/.project b/FreedomStudio/E51FPGA/global_interrupts/.project
deleted file mode 100644
index 32aca6a..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/.project
+++ /dev/null
@@ -1,353 +0,0 @@
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- <name>bsp/include/sifive/devices/uart.h</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
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-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
deleted file mode 100644
index 6a7abd3..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv64&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/global_interrupts.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="global_interrupts"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/global_interrupts"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/global_interrupts/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/local_interrupts/.cproject b/FreedomStudio/E51FPGA/local_interrupts/.cproject
deleted file mode 100644
index 672c12d..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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diff --git a/FreedomStudio/E51FPGA/local_interrupts/.gitignore b/FreedomStudio/E51FPGA/local_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/local_interrupts/.project b/FreedomStudio/E51FPGA/local_interrupts/.project
deleted file mode 100644
index e70b49a..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/.project
+++ /dev/null
@@ -1,353 +0,0 @@
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
deleted file mode 100644
index e03495c..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv64&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
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-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
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-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/local_interrupts.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="local_interrupts"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
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-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/local_interrupts"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/performance_counters/.cproject b/FreedomStudio/E51FPGA/performance_counters/.cproject
deleted file mode 100644
index 6a5801a..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/.cproject
+++ /dev/null
@@ -1,208 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1145706094" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.more" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.120899886" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.1496840810" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.446955466" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
- </tool>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1446800331" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.917780362" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1881705446" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.453203469" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.511548754" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.1318187086" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1829288149" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.663740155" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" value="true" valueType="boolean"/>
- </tool>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1315189209" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1728208687" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format"/>
- </tool>
- </toolChain>
- </folderInfo>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
- </cconfiguration>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="coreplexip_welcome.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.84799689" name="Executable" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
- </storageModule>
- <storageModule moduleId="scannerConfiguration">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.743554394;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2132640858">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- </scannerConfigBuildInfo>
- <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.424460842;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1695943366">
- <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
- </scannerConfigBuildInfo>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
- <storageModule moduleId="refreshScope" versionNumber="2">
- <configuration configurationName="Debug">
- <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
- </configuration>
- <configuration configurationName="Release">
- <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
- </configuration>
- </storageModule>
- <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-</cproject>
diff --git a/FreedomStudio/E51FPGA/performance_counters/.gitignore b/FreedomStudio/E51FPGA/performance_counters/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/performance_counters/.project b/FreedomStudio/E51FPGA/performance_counters/.project
deleted file mode 100644
index ab25a9b..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/.project
+++ /dev/null
@@ -1,353 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>performance_counters</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <linkedResources>
- <link>
- <name>bsp</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>performance_counters.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/performance_counters/performance_counters.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-arty.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
- </link>
- <link>
- <name>bsp/env/entry.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
- </link>
- <link>
- <name>bsp/env/hifive1.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
- </link>
- <link>
- <name>bsp/env/start.S</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c</locationURI>
- </link>
- <link>
- <name>bsp/drivers/plic/plic_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty/scratchpad.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/scratchpad.lds</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json b/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
deleted file mode 100644
index 75f80ba..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv64&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e51-arty.cfg"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/performance_counters.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="performance_counters"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/performance_counters"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;&lt;memoryBlockExpression address=&quot;2147483648&quot; label=&quot;0x80000000&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/performance_counters/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
deleted file mode 100644
index 747f474..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
+++ /dev/null
@@ -1,211 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722">
- <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" moduleId="org.eclipse.cdt.core.settings" name="Debug">
- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash.1442629066" name="Create flash image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1145706094" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.debug" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.120899886" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.1496840810" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections.1701706933" name="Data sections (-fdata-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections" useByScannerDiscovery="true" value="false" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.745111521" name="Debug level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.max" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format.1611143071" name="Debug format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.format" useByScannerDiscovery="true"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name.1877960829" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.toolchain.name" useByScannerDiscovery="false" value="RISC-V GCC/Newlib" valueType="string"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix.762982118" name="Prefix" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix" useByScannerDiscovery="false" value="riscv64-unknown-elf-" valueType="string"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c.762197847" name="C compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.1524666999" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1788482879" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv64i" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
- <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
- <builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
- <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1772574500" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1451354185" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths.2050116277" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../../../../bsp/include"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env"/>
- <listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
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diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore b/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.project b/FreedomStudio/E51FPGA/vectored_interrupts/.project
deleted file mode 100644
index f83b549..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.project
+++ /dev/null
@@ -1,353 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>vectored_interrupts</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
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- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <linkedResources>
- <link>
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- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/software/vectored_interrupts/vectored_interrupts.c</locationURI>
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- <link>
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- </link>
- <link>
- <name>bsp/drivers/plic</name>
- <type>2</type>
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- <link>
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- </link>
- <link>
- <name>bsp/env/coreplexip-e51-arty</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/env/encoding.h</name>
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- <type>2</type>
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- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
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- <link>
- <name>bsp/drivers/fe300prci/fe300prci_driver.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI>
- </link>
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- <link>
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- <name>bsp/include/sifive/devices/gpio.h</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
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- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
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- <link>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
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- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
deleted file mode 100644
index aac7a77..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
+++ /dev/null
@@ -1,1230 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "e51arty": {
- "displayName": "Core Complex E51 Arty",
- "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "64",
- "resetMask": "all",
- "resetValue": "0x0000000000000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
- "headerTypePrefix": "sifive_e51arty_",
- "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "26",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e51": {
- "harts": "1",
- "isa": "RV64IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- },
- "0": {
- "description": "Local Interrupt 0",
- "value": "16"
- },
- "1": {
- "description": "Local Interrupt 1",
- "value": "17"
- },
- "2": {
- "description": "Local Interrupt 2",
- "value": "18"
- },
- "3": {
- "description": "Local Interrupt 3",
- "value": "19"
- },
- "4": {
- "description": "Local Interrupt 4",
- "value": "20"
- },
- "5": {
- "description": "Local Interrupt 5",
- "value": "21"
- },
- "6": {
- "description": "Local Interrupt 6",
- "value": "22"
- },
- "7": {
- "description": "Local Interrupt 7",
- "value": "23"
- },
- "8": {
- "description": "Local Interrupt 8",
- "value": "24"
- },
- "9": {
- "description": "Local Interrupt 9",
- "value": "25"
- },
- "10": {
- "description": "Local Interrupt 10",
- "value": "26"
- },
- "11": {
- "description": "Local Interrupt 11",
- "value": "27"
- },
- "12": {
- "description": "Local Interrupt 12",
- "value": "28"
- },
- "13": {
- "description": "Local Interrupt 13",
- "value": "29"
- },
- "14": {
- "description": "Local Interrupt 14",
- "value": "30"
- },
- "15": {
- "description": "Local Interrupt 15",
- "value": "31"
- }
- },
- "numLocalInterrupts": "16"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- },
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "regWidth": "64"
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "regWidth": "64"
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "27",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "16",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "16",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- },
- "interrupts": {
- "switch0": {
- "description": "SWITCH 0 Interrupt",
- "value": "2"
- },
- "switch1": {
- "description": "SWITCH 1 Interrupt",
- "value": "3"
- },
- "switch2": {
- "description": "SWITCH 2 Interrupt",
- "value": "4"
- },
- "switch3": {
- "description": "SWITCH 3 Interrupt",
- "value": "5"
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x20002000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "7"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "8"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "9"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "10"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "11"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "12"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "13"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "14"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "15"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "16"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "17"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "18"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "19"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "20"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "21"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "22"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x20000000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "1"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x20004000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x20005000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "23"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "24"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "25"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "26"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg
deleted file mode 100644
index 8b382dc..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# JTAG adapter setup
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-# Un-comment these two flash lines if you have a SPI flash and want to write
-# it.
-flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
-init
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
-}
-halt
-flash protect 0 64 last off
-echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
deleted file mode 100644
index 6d29781..0000000
--- a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/demo_gpio/.cproject b/FreedomStudio/HiFive1/demo_gpio/.cproject
deleted file mode 100644
index ab6f99e..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/.cproject
+++ /dev/null
@@ -1,211 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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- <externalSettings/>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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- <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug">
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diff --git a/FreedomStudio/HiFive1/demo_gpio/.gitignore b/FreedomStudio/HiFive1/demo_gpio/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/HiFive1/demo_gpio/.project b/FreedomStudio/HiFive1/demo_gpio/.project
deleted file mode 100644
index 0e42de2..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/.project
+++ /dev/null
@@ -1,348 +0,0 @@
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
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- <type>1</type>
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- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
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- <type>1</type>
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- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
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- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch b/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch
deleted file mode 100644
index daada7b..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-freedom-e300-hifive1.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
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-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
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-<listEntry value="/demo_gpio"/>
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-<listEntry value="4"/>
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diff --git a/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json b/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json
deleted file mode 100644
index 1722e54..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json
+++ /dev/null
@@ -1,2325 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "fe310": {
- "displayName": "Freedom E310-G000",
- "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
- "headerTypePrefix": "sifive_fe310_",
- "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "51",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- }
- },
- "numLocalInterrupts": "0"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "52",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "2",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "2",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- }
- },
- "wdog": {
- "description": "Watchdog Timer (WDT), part of Always-On Domain",
- "baseAddress": "0x10000000",
- "size": "0x0040",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Watchdog Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "Watchdog counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "rsten": {
- "description": "Watchdog full reset enable",
- "bitOffset": "8",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "zerocmp": {
- "description": "Watchdog zero on comparator",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Watchdog enable counter always",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "encoreawake": {
- "description": "Watchdog counter only when awake",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "Watchdog interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Watchdog Count Register",
- "addressOffset": "0x0008"
- },
- "scale": {
- "description": "Watchdog Scale Register",
- "addressOffset": "0x0010",
- "fields": {
- "value": {
- "description": "Watchdog scale value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "feed": {
- "description": "Watchdog Feed Address Register",
- "addressOffset": "0x0018"
- },
- "key": {
- "description": "Watchdog Key Register",
- "addressOffset": "0x001C"
- },
- "cmp": {
- "description": "Watchdog Compare Register",
- "addressOffset": "0x0020",
- "fields": {
- "value": {
- "description": "Watchdog compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "wdogcmp": {
- "description": "Watchdog Compare Interrupt",
- "value": "1"
- }
- }
- },
- "rtc": {
- "description": "Real-Time Clock (RTC), part of Always-On Domain",
- "baseAddress": "0x10000040",
- "size": "0x0030",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "RTC Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "RTC clock rate scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "enalways": {
- "description": "RTC counter enable",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "RTC comparator interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "low": {
- "description": "RTC Counter Register Low",
- "addressOffset": "0x0008"
- },
- "high": {
- "description": "RTC Counter Register High",
- "addressOffset": "0x000C",
- "fields": {
- "value": {
- "description": "RTC counter register, high bits",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "scale": {
- "description": "RTC Scale Register",
- "addressOffset": "0x0010"
- },
- "cmp": {
- "description": "RTC Compare Register",
- "addressOffset": "0x0020"
- }
- },
- "interrupts": {
- "rtccmp": {
- "description": "RTC Compare Interrupt",
- "value": "2"
- }
- }
- },
- "pmu": {
- "description": "Power-Management Unit (PMU), part of Always-On Domain",
- "baseAddress": "0x10000100",
- "size": "0x0050",
- "resetMask": "none",
- "registers": {
- "wakeupi": {
- "description": "Wakeup program instruction Registers",
- "addressOffset": "0x0000",
- "arraySize": "8"
- },
- "sleepi": {
- "description": "Sleep Program Instruction Registers",
- "addressOffset": "0x0020",
- "arraySize": "8"
- },
- "ie": {
- "description": "PMU Interrupt Enables Register",
- "addressOffset": "0x0040",
- "fields": {
- "rtc": {
- "description": "RTC Comparator active",
- "bitOffset": "1",
- "bitWidth": "1"
- },
- "dwakeup": {
- "description": "dwakeup_n pin active",
- "bitOffset": "2",
- "bitWidth": "1"
- }
- }
- },
- "cause": {
- "description": "PMU Wakeup Cause Register",
- "addressOffset": "0x0044",
- "fields": {
- "wakeupcause": {
- "description": "Wakeup cause",
- "bitOffset": "0",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "wakeupcause-enum": {
- "description": "Wakeup Cause Values Enumeration",
- "values": {
- "0": {
- "displayName": "reset",
- "description": "Reset Wakeup"
- },
- "1": {
- "displayName": "rtc",
- "description": "RTC Wakeup"
- },
- "2": {
- "displayName": "dwakeup",
- "description": "Digital input Wakeup"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- },
- "resetcause": {
- "description": "Reset cause",
- "bitOffset": "8",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "resetcause-enum": {
- "description": "Reset Cause Values Enumeration",
- "values": {
- "1": {
- "displayName": "external",
- "description": "External reset"
- },
- "2": {
- "displayName": "watchdog",
- "description": "Watchdog timer reset"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- }
- }
- },
- "sleep": {
- "description": "PMU Initiate Sleep Sequence Register",
- "addressOffset": "0x0048"
- },
- "key": {
- "description": "PMU Key Register",
- "addressOffset": "0x004C"
- }
- }
- },
- "aon": {
- "description": "Always-On (AON) Domain",
- "baseAddress": "0x10000070",
- "size": "0x0090",
- "resetMask": "none",
- "registers": {
- "lfrosccfg": {
- "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "LFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "LFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "LFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "LFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "backup": {
- "description": "Backup Registers",
- "addressOffset": "0x0010",
- "arraySize": "32"
- }
- }
- },
- "prci": {
- "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
- "baseAddress": "0x10008000",
- "size": "0x8000",
- "registers": {
- "hfrosccfg": {
- "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "HFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "HFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "HFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "hfxosccfg": {
- "description": "External 16 MHz Crystal Oscillator Register",
- "addressOffset": "0x0004",
- "fields": {
- "en": {
- "description": "HFXOSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFXOSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "pllcfg": {
- "description": "Internal High-Frequency PLL (HFPLL) Register",
- "addressOffset": "0x0008",
- "fields": {
- "r": {
- "description": "PLL R input divider value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "pllr-enum": {
- "description": "Reference Clock R Divide Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "/1",
- "headerName": "div1",
- "description": "Unchanged"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/3",
- "headerName": "div3",
- "description": "Divided by 3"
- },
- "3": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- }
- }
- }
- }
- },
- "f": {
- "description": "PLL F multiplier value",
- "bitOffset": "4",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x1F",
- "enumerations": {
- "pllf-enum": {
- "description": "Reference Clock F Multiplier Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "*2",
- "headerName": "mul2",
- "description": "Multiplied by 2"
- },
- "1": {
- "displayName": "*4",
- "headerName": "mul4",
- "description": "Multiplied by 4"
- },
- "2": {
- "displayName": "*6",
- "headerName": "mul6",
- "description": "Multiplied by 6"
- },
- "3": {
- "displayName": "*8",
- "headerName": "mul8",
- "description": "Multiplied by 8"
- },
- "4": {
- "displayName": "*10",
- "headerName": "mul10",
- "description": "Multiplied by 10"
- },
- "5": {
- "displayName": "*12",
- "headerName": "mul12",
- "description": "Multiplied by 12"
- },
- "6": {
- "displayName": "*14",
- "headerName": "mul14",
- "description": "Multiplied by 14"
- },
- "7": {
- "displayName": "*16",
- "headerName": "mul16",
- "description": "Multiplied by 16"
- },
- "8": {
- "displayName": "*18",
- "headerName": "mul18",
- "description": "Multiplied by 18"
- },
- "9": {
- "displayName": "*20",
- "headerName": "mul20",
- "description": "Multiplied by 20"
- },
- "10": {
- "displayName": "*22",
- "headerName": "mul22",
- "description": "Multiplied by 22"
- },
- "11": {
- "displayName": "*24",
- "headerName": "mul24",
- "description": "Multiplied by 24"
- },
- "12": {
- "displayName": "*26",
- "headerName": "mul26",
- "description": "Multiplied by 26"
- },
- "13": {
- "displayName": "*28",
- "headerName": "mul28",
- "description": "Multiplied by 28"
- },
- "14": {
- "displayName": "*30",
- "headerName": "mul30",
- "description": "Multiplied by 30"
- },
- "15": {
- "displayName": "*32",
- "headerName": "mul32",
- "description": "Multiplied by 32"
- },
- "16": {
- "displayName": "*34",
- "headerName": "mul34",
- "description": "Multiplied by 34"
- },
- "17": {
- "displayName": "*36",
- "headerName": "mul36",
- "description": "Multiplied by 36"
- },
- "18": {
- "displayName": "*38",
- "headerName": "mul38",
- "description": "Multiplied by 38"
- },
- "19": {
- "displayName": "*40",
- "headerName": "mul40",
- "description": "Multiplied by 40"
- },
- "20": {
- "displayName": "*42",
- "headerName": "mul42",
- "description": "Multiplied by 42"
- },
- "21": {
- "displayName": "*44",
- "headerName": "mul44",
- "description": "Multiplied by 44"
- },
- "22": {
- "displayName": "*46",
- "headerName": "mul46",
- "description": "Multiplied by 46"
- },
- "23": {
- "displayName": "*48",
- "headerName": "mul48",
- "description": "Multiplied by 48"
- },
- "24": {
- "displayName": "*50",
- "headerName": "mul50",
- "description": "Multiplied by 50"
- },
- "25": {
- "displayName": "*52",
- "headerName": "mul52",
- "description": "Multiplied by 52"
- },
- "26": {
- "displayName": "*54",
- "headerName": "mul54",
- "description": "Multiplied by 54"
- },
- "27": {
- "displayName": "*56",
- "headerName": "mul56",
- "description": "Multiplied by 56"
- },
- "28": {
- "displayName": "*58",
- "headerName": "mul58",
- "description": "Multiplied by 58"
- },
- "29": {
- "displayName": "*60",
- "headerName": "mul60",
- "description": "Multiplied by 60"
- },
- "30": {
- "displayName": "*62",
- "headerName": "mul62",
- "description": "Multiplied by 62"
- },
- "31": {
- "displayName": "*64",
- "headerName": "mul64",
- "description": "Multiplied by 64"
- },
- "32": {
- "displayName": "*66",
- "headerName": "mul66",
- "description": "Multiplied by 66"
- },
- "33": {
- "displayName": "*68",
- "headerName": "mul68",
- "description": "Multiplied by 68"
- },
- "34": {
- "displayName": "*70",
- "headerName": "mul70",
- "description": "Multiplied by 70"
- },
- "35": {
- "displayName": "*72",
- "headerName": "mul72",
- "description": "Multiplied by 72"
- },
- "36": {
- "displayName": "*74",
- "headerName": "mul74",
- "description": "Multiplied by 74"
- },
- "37": {
- "displayName": "*76",
- "headerName": "mul76",
- "description": "Multiplied by 76"
- },
- "38": {
- "displayName": "*78",
- "headerName": "mul78",
- "description": "Multiplied by 78"
- },
- "39": {
- "displayName": "*80",
- "headerName": "mul80",
- "description": "Multiplied by 80"
- },
- "40": {
- "displayName": "*82",
- "headerName": "mul82",
- "description": "Multiplied by 82"
- },
- "41": {
- "displayName": "*84",
- "headerName": "mul84",
- "description": "Multiplied by 84"
- },
- "42": {
- "displayName": "*86",
- "headerName": "mul86",
- "description": "Multiplied by 86"
- },
- "43": {
- "displayName": "*88",
- "headerName": "mul88",
- "description": "Multiplied by 88"
- },
- "44": {
- "displayName": "*90",
- "headerName": "mul90",
- "description": "Multiplied by 90"
- },
- "45": {
- "displayName": "*92",
- "headerName": "mul92",
- "description": "Multiplied by 92"
- },
- "46": {
- "displayName": "*94",
- "headerName": "mul94",
- "description": "Multiplied by 94"
- },
- "47": {
- "displayName": "*96",
- "headerName": "mul96",
- "description": "Multiplied by 96"
- },
- "48": {
- "displayName": "*98",
- "headerName": "mul98",
- "description": "Multiplied by 98"
- },
- "49": {
- "displayName": "*100",
- "headerName": "mul100",
- "description": "Multiplied by 100"
- },
- "50": {
- "displayName": "*102",
- "headerName": "mul102",
- "description": "Multiplied by 102"
- },
- "51": {
- "displayName": "*104",
- "headerName": "mul104",
- "description": "Multiplied by 104"
- },
- "52": {
- "displayName": "*106",
- "headerName": "mul106",
- "description": "Multiplied by 106"
- },
- "53": {
- "displayName": "*108",
- "headerName": "mul108",
- "description": "Multiplied by 108"
- },
- "54": {
- "displayName": "*110",
- "headerName": "mul110",
- "description": "Multiplied by 110"
- },
- "55": {
- "displayName": "*112",
- "headerName": "mul112",
- "description": "Multiplied by 112"
- },
- "56": {
- "displayName": "*114",
- "headerName": "mul114",
- "description": "Multiplied by 114"
- },
- "57": {
- "displayName": "*116",
- "headerName": "mul116",
- "description": "Multiplied by 116"
- },
- "58": {
- "displayName": "*118",
- "headerName": "mul118",
- "description": "Multiplied by 118"
- },
- "59": {
- "displayName": "*120",
- "headerName": "mul120",
- "description": "Multiplied by 120"
- },
- "60": {
- "displayName": "*122",
- "headerName": "mul122",
- "description": "Multiplied by 122"
- },
- "61": {
- "displayName": "*124",
- "headerName": "mul124",
- "description": "Multiplied by 124"
- },
- "62": {
- "displayName": "*126",
- "headerName": "mul126",
- "description": "Multiplied by 126"
- },
- "63": {
- "displayName": "*128",
- "headerName": "mul128",
- "description": "Multiplied by 128"
- }
- }
- }
- }
- },
- "q": {
- "description": "PLL Q output divider value",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x3",
- "enumerations": {
- "pllq-enum": {
- "description": "Reference Clock Q Divide Ratio Enumeration",
- "values": {
- "*": {
- "displayName": "n/a",
- "description": "Not supported"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- },
- "3": {
- "displayName": "/8",
- "headerName": "div8",
- "description": "Divided by 8"
- }
- }
- }
- }
- },
- "sel": {
- "description": "PLL select",
- "bitOffset": "16",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "refsel": {
- "description": "PLL reference select",
- "bitOffset": "17",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "bypass": {
- "description": "PLL bypass",
- "bitOffset": "18",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "lock": {
- "description": "PLL lock indicator",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "plloutdiv": {
- "description": "PLL Output Divider",
- "addressOffset": "0x000C"
- }
- }
- },
- "otp": {
- "description": "One-Time Programmable Memory (OTP) Peripheral",
- "baseAddress": "0x10010000",
- "size": "0x1000",
- "registers": {
- "lock": {
- "description": "Programmed-I/O Lock Register",
- "addressOffset": "0x0000"
- },
- "ck": {
- "description": "Device Clock Signal Register",
- "addressOffset": "0x0004"
- },
- "oe": {
- "description": "Device Output-Enable Signal Register",
- "addressOffset": "0x0008"
- },
- "sel": {
- "description": "Device Chip-Select Signal Register",
- "addressOffset": "0x000C"
- },
- "we": {
- "description": "Device Write-Enable Signal Register",
- "addressOffset": "0x0010"
- },
- "mr": {
- "description": "Device Mode Register",
- "addressOffset": "0x0014"
- },
- "mrr": {
- "description": "Read-Voltage Regulator Control Register",
- "addressOffset": "0x0018"
- },
- "mpp": {
- "description": "Write-Voltage Charge Pump Control Register",
- "addressOffset": "0x001C"
- },
- "vrren": {
- "description": "Read-Voltage Enable Register",
- "addressOffset": "0x0020"
- },
- "vppen": {
- "description": "Write-Voltage Enable Register",
- "addressOffset": "0x0024"
- },
- "a": {
- "description": "Device Address Register",
- "addressOffset": "0x0028"
- },
- "d": {
- "description": "Device Data Input Register",
- "addressOffset": "0x002C"
- },
- "q": {
- "description": "Device Data Output Register",
- "addressOffset": "0x0030"
- },
- "rsctrl": {
- "description": "Read Sequencer Control Register",
- "addressOffset": "0x0034",
- "fields": {
- "scale": {
- "description": "OTP timescale",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "tas": {
- "description": "Address setup time",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "trp": {
- "description": "Read pulse time",
- "bitOffset": "4",
- "bitWidth": "1"
- },
- "tracc": {
- "description": "Read access time",
- "bitOffset": "5",
- "bitWidth": "1"
- }
- }
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x10012000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "8"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "9"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "10"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "11"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "12"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "13"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "14"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "15"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "16"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "17"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "18"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "19"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "20"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "21"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "22"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "23"
- },
- "gpio16": {
- "description": "GPIO16 Interrupt",
- "value": "24"
- },
- "gpio17": {
- "description": "GPIO17 Interrupt",
- "value": "25"
- },
- "gpio18": {
- "description": "GPIO18 Interrupt",
- "value": "26"
- },
- "gpio19": {
- "description": "GPIO19 Interrupt",
- "value": "27"
- },
- "gpio20": {
- "description": "GPIO20 Interrupt",
- "value": "28"
- },
- "gpio21": {
- "description": "GPIO21 Interrupt",
- "value": "29"
- },
- "gpio22": {
- "description": "GPIO22 Interrupt",
- "value": "30"
- },
- "gpio23": {
- "description": "GPIO23 Interrupt",
- "value": "31"
- },
- "gpio24": {
- "description": "GPIO24 Interrupt",
- "value": "32"
- },
- "gpio25": {
- "description": "GPIO25 Interrupt",
- "value": "33"
- },
- "gpio26": {
- "description": "GPIO26 Interrupt",
- "value": "34"
- },
- "gpio27": {
- "description": "GPIO27 Interrupt",
- "value": "35"
- },
- "gpio28": {
- "description": "GPIO28 Interrupt",
- "value": "36"
- },
- "gpio29": {
- "description": "GPIO29 Interrupt",
- "value": "37"
- },
- "gpio30": {
- "description": "GPIO30 Interrupt",
- "value": "38"
- },
- "gpio31": {
- "description": "GPIO31 Interrupt",
- "value": "39"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x10013000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "3"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x10014000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "5"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10015000",
- "size": "0x1000",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "40"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "41"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "42"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "43"
- }
- }
- },
- "uart1": {
- "baseAddress": "0x10023000",
- "derivedFrom": "uart0",
- "groupName": "uart",
- "interrupts": {
- "uart1": {
- "description": "UART1 Interrupt",
- "value": "4"
- }
- }
- },
- "spi1": {
- "baseAddress": "0x10024000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi1": {
- "description": "SPI1 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm1": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10025000",
- "groupName": "pwm",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "pwm1cmp0": {
- "description": "PWM1 Compare 0 Interrupt",
- "value": "44"
- },
- "pwm1cmp1": {
- "description": "PWM1 Compare 1 Interrupt",
- "value": "45"
- },
- "pwm1cmp2": {
- "description": "PWM1 Compare 2 Interrupt",
- "value": "46"
- },
- "pwm1cmp3": {
- "description": "PWM1 Compare 3 Interrupt",
- "value": "47"
- }
- }
- },
- "spi2": {
- "baseAddress": "0x10034000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi2": {
- "description": "SPI2 Interrupt",
- "value": "7"
- }
- }
- },
- "pwm2": {
- "baseAddress": "0x10035000",
- "derivedFrom": "pwm1",
- "groupName": "pwm",
- "interrupts": {
- "pwm2cmp0": {
- "description": "PWM2 Compare 0 Interrupt",
- "value": "48"
- },
- "pwm2cmp1": {
- "description": "PWM2 Compare 1 Interrupt",
- "value": "49"
- },
- "pwm2cmp2": {
- "description": "PWM2 Compare 2 Interrupt",
- "value": "50"
- },
- "pwm2cmp3": {
- "description": "PWM2 Compare 3 Interrupt",
- "value": "51"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg
deleted file mode 100644
index b0a8e26..0000000
--- a/FreedomStudio/HiFive1/demo_gpio/sifive-freedom-e300-hifive1.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
- #Wait for the reset stretcher
- #It will work without this, but
- #will incur lots of delays for later commands.
- sleep 1500
-}
-halt
-flash protect 0 64 last off
diff --git a/FreedomStudio/HiFive1/dhrystone/.cproject b/FreedomStudio/HiFive1/dhrystone/.cproject
deleted file mode 100644
index ca95225..0000000
--- a/FreedomStudio/HiFive1/dhrystone/.cproject
+++ /dev/null
@@ -1,211 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/dhrystone/.gitignore b/FreedomStudio/HiFive1/dhrystone/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/HiFive1/dhrystone/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/HiFive1/dhrystone/.project b/FreedomStudio/HiFive1/dhrystone/.project
deleted file mode 100644
index 040d41a..0000000
--- a/FreedomStudio/HiFive1/dhrystone/.project
+++ /dev/null
@@ -1,368 +0,0 @@
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/dhrystone.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/dhrystone.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/flash.lds</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/flash.lds</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/init.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/init.c</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/openocd.cfg</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/openocd.cfg</locationURI>
- </link>
- <link>
- <name>bsp/env/freedom-e300-hifive1/platform.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/platform.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/bits.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/const.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/sections.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/smp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/puts.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/sbrk.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/weak_under_alias.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
- </link>
- <link>
- <name>bsp/libwrap/sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/aon.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/clint.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/gpio.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/otp.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/plic.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/prci.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/pwm.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/spi.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI>
- </link>
- <link>
- <name>bsp/include/sifive/devices/uart.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
- </link>
- </linkedResources>
-</projectDescription>
diff --git a/FreedomStudio/HiFive1/dhrystone/dhrystone.launch b/FreedomStudio/HiFive1/dhrystone/dhrystone.launch
deleted file mode 100644
index 57e1418..0000000
--- a/FreedomStudio/HiFive1/dhrystone/dhrystone.launch
+++ /dev/null
@@ -1,61 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-freedom-e300-hifive1.cfg"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/dhrystone.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dhrystone"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/dhrystone"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/HiFive1/dhrystone/fe310-xsvd.json b/FreedomStudio/HiFive1/dhrystone/fe310-xsvd.json
deleted file mode 100644
index 1722e54..0000000
--- a/FreedomStudio/HiFive1/dhrystone/fe310-xsvd.json
+++ /dev/null
@@ -1,2325 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "fe310": {
- "displayName": "Freedom E310-G000",
- "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
- "headerTypePrefix": "sifive_fe310_",
- "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "51",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- }
- },
- "numLocalInterrupts": "0"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "52",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "2",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "2",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- }
- },
- "wdog": {
- "description": "Watchdog Timer (WDT), part of Always-On Domain",
- "baseAddress": "0x10000000",
- "size": "0x0040",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Watchdog Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "Watchdog counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "rsten": {
- "description": "Watchdog full reset enable",
- "bitOffset": "8",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "zerocmp": {
- "description": "Watchdog zero on comparator",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Watchdog enable counter always",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "encoreawake": {
- "description": "Watchdog counter only when awake",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "Watchdog interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Watchdog Count Register",
- "addressOffset": "0x0008"
- },
- "scale": {
- "description": "Watchdog Scale Register",
- "addressOffset": "0x0010",
- "fields": {
- "value": {
- "description": "Watchdog scale value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "feed": {
- "description": "Watchdog Feed Address Register",
- "addressOffset": "0x0018"
- },
- "key": {
- "description": "Watchdog Key Register",
- "addressOffset": "0x001C"
- },
- "cmp": {
- "description": "Watchdog Compare Register",
- "addressOffset": "0x0020",
- "fields": {
- "value": {
- "description": "Watchdog compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "wdogcmp": {
- "description": "Watchdog Compare Interrupt",
- "value": "1"
- }
- }
- },
- "rtc": {
- "description": "Real-Time Clock (RTC), part of Always-On Domain",
- "baseAddress": "0x10000040",
- "size": "0x0030",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "RTC Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "RTC clock rate scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "enalways": {
- "description": "RTC counter enable",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "RTC comparator interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "low": {
- "description": "RTC Counter Register Low",
- "addressOffset": "0x0008"
- },
- "high": {
- "description": "RTC Counter Register High",
- "addressOffset": "0x000C",
- "fields": {
- "value": {
- "description": "RTC counter register, high bits",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "scale": {
- "description": "RTC Scale Register",
- "addressOffset": "0x0010"
- },
- "cmp": {
- "description": "RTC Compare Register",
- "addressOffset": "0x0020"
- }
- },
- "interrupts": {
- "rtccmp": {
- "description": "RTC Compare Interrupt",
- "value": "2"
- }
- }
- },
- "pmu": {
- "description": "Power-Management Unit (PMU), part of Always-On Domain",
- "baseAddress": "0x10000100",
- "size": "0x0050",
- "resetMask": "none",
- "registers": {
- "wakeupi": {
- "description": "Wakeup program instruction Registers",
- "addressOffset": "0x0000",
- "arraySize": "8"
- },
- "sleepi": {
- "description": "Sleep Program Instruction Registers",
- "addressOffset": "0x0020",
- "arraySize": "8"
- },
- "ie": {
- "description": "PMU Interrupt Enables Register",
- "addressOffset": "0x0040",
- "fields": {
- "rtc": {
- "description": "RTC Comparator active",
- "bitOffset": "1",
- "bitWidth": "1"
- },
- "dwakeup": {
- "description": "dwakeup_n pin active",
- "bitOffset": "2",
- "bitWidth": "1"
- }
- }
- },
- "cause": {
- "description": "PMU Wakeup Cause Register",
- "addressOffset": "0x0044",
- "fields": {
- "wakeupcause": {
- "description": "Wakeup cause",
- "bitOffset": "0",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "wakeupcause-enum": {
- "description": "Wakeup Cause Values Enumeration",
- "values": {
- "0": {
- "displayName": "reset",
- "description": "Reset Wakeup"
- },
- "1": {
- "displayName": "rtc",
- "description": "RTC Wakeup"
- },
- "2": {
- "displayName": "dwakeup",
- "description": "Digital input Wakeup"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- },
- "resetcause": {
- "description": "Reset cause",
- "bitOffset": "8",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "resetcause-enum": {
- "description": "Reset Cause Values Enumeration",
- "values": {
- "1": {
- "displayName": "external",
- "description": "External reset"
- },
- "2": {
- "displayName": "watchdog",
- "description": "Watchdog timer reset"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- }
- }
- },
- "sleep": {
- "description": "PMU Initiate Sleep Sequence Register",
- "addressOffset": "0x0048"
- },
- "key": {
- "description": "PMU Key Register",
- "addressOffset": "0x004C"
- }
- }
- },
- "aon": {
- "description": "Always-On (AON) Domain",
- "baseAddress": "0x10000070",
- "size": "0x0090",
- "resetMask": "none",
- "registers": {
- "lfrosccfg": {
- "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "LFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "LFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "LFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "LFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "backup": {
- "description": "Backup Registers",
- "addressOffset": "0x0010",
- "arraySize": "32"
- }
- }
- },
- "prci": {
- "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
- "baseAddress": "0x10008000",
- "size": "0x8000",
- "registers": {
- "hfrosccfg": {
- "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "HFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "HFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "HFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "hfxosccfg": {
- "description": "External 16 MHz Crystal Oscillator Register",
- "addressOffset": "0x0004",
- "fields": {
- "en": {
- "description": "HFXOSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFXOSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "pllcfg": {
- "description": "Internal High-Frequency PLL (HFPLL) Register",
- "addressOffset": "0x0008",
- "fields": {
- "r": {
- "description": "PLL R input divider value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "pllr-enum": {
- "description": "Reference Clock R Divide Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "/1",
- "headerName": "div1",
- "description": "Unchanged"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/3",
- "headerName": "div3",
- "description": "Divided by 3"
- },
- "3": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- }
- }
- }
- }
- },
- "f": {
- "description": "PLL F multiplier value",
- "bitOffset": "4",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x1F",
- "enumerations": {
- "pllf-enum": {
- "description": "Reference Clock F Multiplier Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "*2",
- "headerName": "mul2",
- "description": "Multiplied by 2"
- },
- "1": {
- "displayName": "*4",
- "headerName": "mul4",
- "description": "Multiplied by 4"
- },
- "2": {
- "displayName": "*6",
- "headerName": "mul6",
- "description": "Multiplied by 6"
- },
- "3": {
- "displayName": "*8",
- "headerName": "mul8",
- "description": "Multiplied by 8"
- },
- "4": {
- "displayName": "*10",
- "headerName": "mul10",
- "description": "Multiplied by 10"
- },
- "5": {
- "displayName": "*12",
- "headerName": "mul12",
- "description": "Multiplied by 12"
- },
- "6": {
- "displayName": "*14",
- "headerName": "mul14",
- "description": "Multiplied by 14"
- },
- "7": {
- "displayName": "*16",
- "headerName": "mul16",
- "description": "Multiplied by 16"
- },
- "8": {
- "displayName": "*18",
- "headerName": "mul18",
- "description": "Multiplied by 18"
- },
- "9": {
- "displayName": "*20",
- "headerName": "mul20",
- "description": "Multiplied by 20"
- },
- "10": {
- "displayName": "*22",
- "headerName": "mul22",
- "description": "Multiplied by 22"
- },
- "11": {
- "displayName": "*24",
- "headerName": "mul24",
- "description": "Multiplied by 24"
- },
- "12": {
- "displayName": "*26",
- "headerName": "mul26",
- "description": "Multiplied by 26"
- },
- "13": {
- "displayName": "*28",
- "headerName": "mul28",
- "description": "Multiplied by 28"
- },
- "14": {
- "displayName": "*30",
- "headerName": "mul30",
- "description": "Multiplied by 30"
- },
- "15": {
- "displayName": "*32",
- "headerName": "mul32",
- "description": "Multiplied by 32"
- },
- "16": {
- "displayName": "*34",
- "headerName": "mul34",
- "description": "Multiplied by 34"
- },
- "17": {
- "displayName": "*36",
- "headerName": "mul36",
- "description": "Multiplied by 36"
- },
- "18": {
- "displayName": "*38",
- "headerName": "mul38",
- "description": "Multiplied by 38"
- },
- "19": {
- "displayName": "*40",
- "headerName": "mul40",
- "description": "Multiplied by 40"
- },
- "20": {
- "displayName": "*42",
- "headerName": "mul42",
- "description": "Multiplied by 42"
- },
- "21": {
- "displayName": "*44",
- "headerName": "mul44",
- "description": "Multiplied by 44"
- },
- "22": {
- "displayName": "*46",
- "headerName": "mul46",
- "description": "Multiplied by 46"
- },
- "23": {
- "displayName": "*48",
- "headerName": "mul48",
- "description": "Multiplied by 48"
- },
- "24": {
- "displayName": "*50",
- "headerName": "mul50",
- "description": "Multiplied by 50"
- },
- "25": {
- "displayName": "*52",
- "headerName": "mul52",
- "description": "Multiplied by 52"
- },
- "26": {
- "displayName": "*54",
- "headerName": "mul54",
- "description": "Multiplied by 54"
- },
- "27": {
- "displayName": "*56",
- "headerName": "mul56",
- "description": "Multiplied by 56"
- },
- "28": {
- "displayName": "*58",
- "headerName": "mul58",
- "description": "Multiplied by 58"
- },
- "29": {
- "displayName": "*60",
- "headerName": "mul60",
- "description": "Multiplied by 60"
- },
- "30": {
- "displayName": "*62",
- "headerName": "mul62",
- "description": "Multiplied by 62"
- },
- "31": {
- "displayName": "*64",
- "headerName": "mul64",
- "description": "Multiplied by 64"
- },
- "32": {
- "displayName": "*66",
- "headerName": "mul66",
- "description": "Multiplied by 66"
- },
- "33": {
- "displayName": "*68",
- "headerName": "mul68",
- "description": "Multiplied by 68"
- },
- "34": {
- "displayName": "*70",
- "headerName": "mul70",
- "description": "Multiplied by 70"
- },
- "35": {
- "displayName": "*72",
- "headerName": "mul72",
- "description": "Multiplied by 72"
- },
- "36": {
- "displayName": "*74",
- "headerName": "mul74",
- "description": "Multiplied by 74"
- },
- "37": {
- "displayName": "*76",
- "headerName": "mul76",
- "description": "Multiplied by 76"
- },
- "38": {
- "displayName": "*78",
- "headerName": "mul78",
- "description": "Multiplied by 78"
- },
- "39": {
- "displayName": "*80",
- "headerName": "mul80",
- "description": "Multiplied by 80"
- },
- "40": {
- "displayName": "*82",
- "headerName": "mul82",
- "description": "Multiplied by 82"
- },
- "41": {
- "displayName": "*84",
- "headerName": "mul84",
- "description": "Multiplied by 84"
- },
- "42": {
- "displayName": "*86",
- "headerName": "mul86",
- "description": "Multiplied by 86"
- },
- "43": {
- "displayName": "*88",
- "headerName": "mul88",
- "description": "Multiplied by 88"
- },
- "44": {
- "displayName": "*90",
- "headerName": "mul90",
- "description": "Multiplied by 90"
- },
- "45": {
- "displayName": "*92",
- "headerName": "mul92",
- "description": "Multiplied by 92"
- },
- "46": {
- "displayName": "*94",
- "headerName": "mul94",
- "description": "Multiplied by 94"
- },
- "47": {
- "displayName": "*96",
- "headerName": "mul96",
- "description": "Multiplied by 96"
- },
- "48": {
- "displayName": "*98",
- "headerName": "mul98",
- "description": "Multiplied by 98"
- },
- "49": {
- "displayName": "*100",
- "headerName": "mul100",
- "description": "Multiplied by 100"
- },
- "50": {
- "displayName": "*102",
- "headerName": "mul102",
- "description": "Multiplied by 102"
- },
- "51": {
- "displayName": "*104",
- "headerName": "mul104",
- "description": "Multiplied by 104"
- },
- "52": {
- "displayName": "*106",
- "headerName": "mul106",
- "description": "Multiplied by 106"
- },
- "53": {
- "displayName": "*108",
- "headerName": "mul108",
- "description": "Multiplied by 108"
- },
- "54": {
- "displayName": "*110",
- "headerName": "mul110",
- "description": "Multiplied by 110"
- },
- "55": {
- "displayName": "*112",
- "headerName": "mul112",
- "description": "Multiplied by 112"
- },
- "56": {
- "displayName": "*114",
- "headerName": "mul114",
- "description": "Multiplied by 114"
- },
- "57": {
- "displayName": "*116",
- "headerName": "mul116",
- "description": "Multiplied by 116"
- },
- "58": {
- "displayName": "*118",
- "headerName": "mul118",
- "description": "Multiplied by 118"
- },
- "59": {
- "displayName": "*120",
- "headerName": "mul120",
- "description": "Multiplied by 120"
- },
- "60": {
- "displayName": "*122",
- "headerName": "mul122",
- "description": "Multiplied by 122"
- },
- "61": {
- "displayName": "*124",
- "headerName": "mul124",
- "description": "Multiplied by 124"
- },
- "62": {
- "displayName": "*126",
- "headerName": "mul126",
- "description": "Multiplied by 126"
- },
- "63": {
- "displayName": "*128",
- "headerName": "mul128",
- "description": "Multiplied by 128"
- }
- }
- }
- }
- },
- "q": {
- "description": "PLL Q output divider value",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x3",
- "enumerations": {
- "pllq-enum": {
- "description": "Reference Clock Q Divide Ratio Enumeration",
- "values": {
- "*": {
- "displayName": "n/a",
- "description": "Not supported"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- },
- "3": {
- "displayName": "/8",
- "headerName": "div8",
- "description": "Divided by 8"
- }
- }
- }
- }
- },
- "sel": {
- "description": "PLL select",
- "bitOffset": "16",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "refsel": {
- "description": "PLL reference select",
- "bitOffset": "17",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "bypass": {
- "description": "PLL bypass",
- "bitOffset": "18",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "lock": {
- "description": "PLL lock indicator",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "plloutdiv": {
- "description": "PLL Output Divider",
- "addressOffset": "0x000C"
- }
- }
- },
- "otp": {
- "description": "One-Time Programmable Memory (OTP) Peripheral",
- "baseAddress": "0x10010000",
- "size": "0x1000",
- "registers": {
- "lock": {
- "description": "Programmed-I/O Lock Register",
- "addressOffset": "0x0000"
- },
- "ck": {
- "description": "Device Clock Signal Register",
- "addressOffset": "0x0004"
- },
- "oe": {
- "description": "Device Output-Enable Signal Register",
- "addressOffset": "0x0008"
- },
- "sel": {
- "description": "Device Chip-Select Signal Register",
- "addressOffset": "0x000C"
- },
- "we": {
- "description": "Device Write-Enable Signal Register",
- "addressOffset": "0x0010"
- },
- "mr": {
- "description": "Device Mode Register",
- "addressOffset": "0x0014"
- },
- "mrr": {
- "description": "Read-Voltage Regulator Control Register",
- "addressOffset": "0x0018"
- },
- "mpp": {
- "description": "Write-Voltage Charge Pump Control Register",
- "addressOffset": "0x001C"
- },
- "vrren": {
- "description": "Read-Voltage Enable Register",
- "addressOffset": "0x0020"
- },
- "vppen": {
- "description": "Write-Voltage Enable Register",
- "addressOffset": "0x0024"
- },
- "a": {
- "description": "Device Address Register",
- "addressOffset": "0x0028"
- },
- "d": {
- "description": "Device Data Input Register",
- "addressOffset": "0x002C"
- },
- "q": {
- "description": "Device Data Output Register",
- "addressOffset": "0x0030"
- },
- "rsctrl": {
- "description": "Read Sequencer Control Register",
- "addressOffset": "0x0034",
- "fields": {
- "scale": {
- "description": "OTP timescale",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "tas": {
- "description": "Address setup time",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "trp": {
- "description": "Read pulse time",
- "bitOffset": "4",
- "bitWidth": "1"
- },
- "tracc": {
- "description": "Read access time",
- "bitOffset": "5",
- "bitWidth": "1"
- }
- }
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x10012000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "8"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "9"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "10"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "11"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "12"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "13"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "14"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "15"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "16"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "17"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "18"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "19"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "20"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "21"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "22"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "23"
- },
- "gpio16": {
- "description": "GPIO16 Interrupt",
- "value": "24"
- },
- "gpio17": {
- "description": "GPIO17 Interrupt",
- "value": "25"
- },
- "gpio18": {
- "description": "GPIO18 Interrupt",
- "value": "26"
- },
- "gpio19": {
- "description": "GPIO19 Interrupt",
- "value": "27"
- },
- "gpio20": {
- "description": "GPIO20 Interrupt",
- "value": "28"
- },
- "gpio21": {
- "description": "GPIO21 Interrupt",
- "value": "29"
- },
- "gpio22": {
- "description": "GPIO22 Interrupt",
- "value": "30"
- },
- "gpio23": {
- "description": "GPIO23 Interrupt",
- "value": "31"
- },
- "gpio24": {
- "description": "GPIO24 Interrupt",
- "value": "32"
- },
- "gpio25": {
- "description": "GPIO25 Interrupt",
- "value": "33"
- },
- "gpio26": {
- "description": "GPIO26 Interrupt",
- "value": "34"
- },
- "gpio27": {
- "description": "GPIO27 Interrupt",
- "value": "35"
- },
- "gpio28": {
- "description": "GPIO28 Interrupt",
- "value": "36"
- },
- "gpio29": {
- "description": "GPIO29 Interrupt",
- "value": "37"
- },
- "gpio30": {
- "description": "GPIO30 Interrupt",
- "value": "38"
- },
- "gpio31": {
- "description": "GPIO31 Interrupt",
- "value": "39"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x10013000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "3"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x10014000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "5"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10015000",
- "size": "0x1000",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "40"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "41"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "42"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "43"
- }
- }
- },
- "uart1": {
- "baseAddress": "0x10023000",
- "derivedFrom": "uart0",
- "groupName": "uart",
- "interrupts": {
- "uart1": {
- "description": "UART1 Interrupt",
- "value": "4"
- }
- }
- },
- "spi1": {
- "baseAddress": "0x10024000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi1": {
- "description": "SPI1 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm1": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10025000",
- "groupName": "pwm",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "pwm1cmp0": {
- "description": "PWM1 Compare 0 Interrupt",
- "value": "44"
- },
- "pwm1cmp1": {
- "description": "PWM1 Compare 1 Interrupt",
- "value": "45"
- },
- "pwm1cmp2": {
- "description": "PWM1 Compare 2 Interrupt",
- "value": "46"
- },
- "pwm1cmp3": {
- "description": "PWM1 Compare 3 Interrupt",
- "value": "47"
- }
- }
- },
- "spi2": {
- "baseAddress": "0x10034000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi2": {
- "description": "SPI2 Interrupt",
- "value": "7"
- }
- }
- },
- "pwm2": {
- "baseAddress": "0x10035000",
- "derivedFrom": "pwm1",
- "groupName": "pwm",
- "interrupts": {
- "pwm2cmp0": {
- "description": "PWM2 Compare 0 Interrupt",
- "value": "48"
- },
- "pwm2cmp1": {
- "description": "PWM2 Compare 1 Interrupt",
- "value": "49"
- },
- "pwm2cmp2": {
- "description": "PWM2 Compare 2 Interrupt",
- "value": "50"
- },
- "pwm2cmp3": {
- "description": "PWM2 Compare 3 Interrupt",
- "value": "51"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg
deleted file mode 100644
index b0a8e26..0000000
--- a/FreedomStudio/HiFive1/dhrystone/sifive-freedom-e300-hifive1.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
- #Wait for the reset stretcher
- #It will work without this, but
- #will incur lots of delays for later commands.
- sleep 1500
-}
-halt
-flash protect 0 64 last off
diff --git a/FreedomStudio/HiFive1/hello/.cproject b/FreedomStudio/HiFive1/hello/.cproject
deleted file mode 100644
index 6fab261..0000000
--- a/FreedomStudio/HiFive1/hello/.cproject
+++ /dev/null
@@ -1,208 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/hello/.gitignore b/FreedomStudio/HiFive1/hello/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/HiFive1/hello/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/Debug/
diff --git a/FreedomStudio/HiFive1/hello/.project b/FreedomStudio/HiFive1/hello/.project
deleted file mode 100644
index 8a86c16..0000000
--- a/FreedomStudio/HiFive1/hello/.project
+++ /dev/null
@@ -1,348 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/hello/fe310-xsvd.json b/FreedomStudio/HiFive1/hello/fe310-xsvd.json
deleted file mode 100644
index 1722e54..0000000
--- a/FreedomStudio/HiFive1/hello/fe310-xsvd.json
+++ /dev/null
@@ -1,2325 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "fe310": {
- "displayName": "Freedom E310-G000",
- "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
- "headerTypePrefix": "sifive_fe310_",
- "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "51",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- }
- },
- "numLocalInterrupts": "0"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "52",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "2",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "2",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- }
- },
- "wdog": {
- "description": "Watchdog Timer (WDT), part of Always-On Domain",
- "baseAddress": "0x10000000",
- "size": "0x0040",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Watchdog Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "Watchdog counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "rsten": {
- "description": "Watchdog full reset enable",
- "bitOffset": "8",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "zerocmp": {
- "description": "Watchdog zero on comparator",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Watchdog enable counter always",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "encoreawake": {
- "description": "Watchdog counter only when awake",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "Watchdog interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Watchdog Count Register",
- "addressOffset": "0x0008"
- },
- "scale": {
- "description": "Watchdog Scale Register",
- "addressOffset": "0x0010",
- "fields": {
- "value": {
- "description": "Watchdog scale value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "feed": {
- "description": "Watchdog Feed Address Register",
- "addressOffset": "0x0018"
- },
- "key": {
- "description": "Watchdog Key Register",
- "addressOffset": "0x001C"
- },
- "cmp": {
- "description": "Watchdog Compare Register",
- "addressOffset": "0x0020",
- "fields": {
- "value": {
- "description": "Watchdog compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "wdogcmp": {
- "description": "Watchdog Compare Interrupt",
- "value": "1"
- }
- }
- },
- "rtc": {
- "description": "Real-Time Clock (RTC), part of Always-On Domain",
- "baseAddress": "0x10000040",
- "size": "0x0030",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "RTC Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "RTC clock rate scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "enalways": {
- "description": "RTC counter enable",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "RTC comparator interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "low": {
- "description": "RTC Counter Register Low",
- "addressOffset": "0x0008"
- },
- "high": {
- "description": "RTC Counter Register High",
- "addressOffset": "0x000C",
- "fields": {
- "value": {
- "description": "RTC counter register, high bits",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "scale": {
- "description": "RTC Scale Register",
- "addressOffset": "0x0010"
- },
- "cmp": {
- "description": "RTC Compare Register",
- "addressOffset": "0x0020"
- }
- },
- "interrupts": {
- "rtccmp": {
- "description": "RTC Compare Interrupt",
- "value": "2"
- }
- }
- },
- "pmu": {
- "description": "Power-Management Unit (PMU), part of Always-On Domain",
- "baseAddress": "0x10000100",
- "size": "0x0050",
- "resetMask": "none",
- "registers": {
- "wakeupi": {
- "description": "Wakeup program instruction Registers",
- "addressOffset": "0x0000",
- "arraySize": "8"
- },
- "sleepi": {
- "description": "Sleep Program Instruction Registers",
- "addressOffset": "0x0020",
- "arraySize": "8"
- },
- "ie": {
- "description": "PMU Interrupt Enables Register",
- "addressOffset": "0x0040",
- "fields": {
- "rtc": {
- "description": "RTC Comparator active",
- "bitOffset": "1",
- "bitWidth": "1"
- },
- "dwakeup": {
- "description": "dwakeup_n pin active",
- "bitOffset": "2",
- "bitWidth": "1"
- }
- }
- },
- "cause": {
- "description": "PMU Wakeup Cause Register",
- "addressOffset": "0x0044",
- "fields": {
- "wakeupcause": {
- "description": "Wakeup cause",
- "bitOffset": "0",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "wakeupcause-enum": {
- "description": "Wakeup Cause Values Enumeration",
- "values": {
- "0": {
- "displayName": "reset",
- "description": "Reset Wakeup"
- },
- "1": {
- "displayName": "rtc",
- "description": "RTC Wakeup"
- },
- "2": {
- "displayName": "dwakeup",
- "description": "Digital input Wakeup"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- },
- "resetcause": {
- "description": "Reset cause",
- "bitOffset": "8",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "resetcause-enum": {
- "description": "Reset Cause Values Enumeration",
- "values": {
- "1": {
- "displayName": "external",
- "description": "External reset"
- },
- "2": {
- "displayName": "watchdog",
- "description": "Watchdog timer reset"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- }
- }
- },
- "sleep": {
- "description": "PMU Initiate Sleep Sequence Register",
- "addressOffset": "0x0048"
- },
- "key": {
- "description": "PMU Key Register",
- "addressOffset": "0x004C"
- }
- }
- },
- "aon": {
- "description": "Always-On (AON) Domain",
- "baseAddress": "0x10000070",
- "size": "0x0090",
- "resetMask": "none",
- "registers": {
- "lfrosccfg": {
- "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "LFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "LFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "LFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "LFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "backup": {
- "description": "Backup Registers",
- "addressOffset": "0x0010",
- "arraySize": "32"
- }
- }
- },
- "prci": {
- "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
- "baseAddress": "0x10008000",
- "size": "0x8000",
- "registers": {
- "hfrosccfg": {
- "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "HFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "HFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "HFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "hfxosccfg": {
- "description": "External 16 MHz Crystal Oscillator Register",
- "addressOffset": "0x0004",
- "fields": {
- "en": {
- "description": "HFXOSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFXOSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "pllcfg": {
- "description": "Internal High-Frequency PLL (HFPLL) Register",
- "addressOffset": "0x0008",
- "fields": {
- "r": {
- "description": "PLL R input divider value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "pllr-enum": {
- "description": "Reference Clock R Divide Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "/1",
- "headerName": "div1",
- "description": "Unchanged"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/3",
- "headerName": "div3",
- "description": "Divided by 3"
- },
- "3": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- }
- }
- }
- }
- },
- "f": {
- "description": "PLL F multiplier value",
- "bitOffset": "4",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x1F",
- "enumerations": {
- "pllf-enum": {
- "description": "Reference Clock F Multiplier Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "*2",
- "headerName": "mul2",
- "description": "Multiplied by 2"
- },
- "1": {
- "displayName": "*4",
- "headerName": "mul4",
- "description": "Multiplied by 4"
- },
- "2": {
- "displayName": "*6",
- "headerName": "mul6",
- "description": "Multiplied by 6"
- },
- "3": {
- "displayName": "*8",
- "headerName": "mul8",
- "description": "Multiplied by 8"
- },
- "4": {
- "displayName": "*10",
- "headerName": "mul10",
- "description": "Multiplied by 10"
- },
- "5": {
- "displayName": "*12",
- "headerName": "mul12",
- "description": "Multiplied by 12"
- },
- "6": {
- "displayName": "*14",
- "headerName": "mul14",
- "description": "Multiplied by 14"
- },
- "7": {
- "displayName": "*16",
- "headerName": "mul16",
- "description": "Multiplied by 16"
- },
- "8": {
- "displayName": "*18",
- "headerName": "mul18",
- "description": "Multiplied by 18"
- },
- "9": {
- "displayName": "*20",
- "headerName": "mul20",
- "description": "Multiplied by 20"
- },
- "10": {
- "displayName": "*22",
- "headerName": "mul22",
- "description": "Multiplied by 22"
- },
- "11": {
- "displayName": "*24",
- "headerName": "mul24",
- "description": "Multiplied by 24"
- },
- "12": {
- "displayName": "*26",
- "headerName": "mul26",
- "description": "Multiplied by 26"
- },
- "13": {
- "displayName": "*28",
- "headerName": "mul28",
- "description": "Multiplied by 28"
- },
- "14": {
- "displayName": "*30",
- "headerName": "mul30",
- "description": "Multiplied by 30"
- },
- "15": {
- "displayName": "*32",
- "headerName": "mul32",
- "description": "Multiplied by 32"
- },
- "16": {
- "displayName": "*34",
- "headerName": "mul34",
- "description": "Multiplied by 34"
- },
- "17": {
- "displayName": "*36",
- "headerName": "mul36",
- "description": "Multiplied by 36"
- },
- "18": {
- "displayName": "*38",
- "headerName": "mul38",
- "description": "Multiplied by 38"
- },
- "19": {
- "displayName": "*40",
- "headerName": "mul40",
- "description": "Multiplied by 40"
- },
- "20": {
- "displayName": "*42",
- "headerName": "mul42",
- "description": "Multiplied by 42"
- },
- "21": {
- "displayName": "*44",
- "headerName": "mul44",
- "description": "Multiplied by 44"
- },
- "22": {
- "displayName": "*46",
- "headerName": "mul46",
- "description": "Multiplied by 46"
- },
- "23": {
- "displayName": "*48",
- "headerName": "mul48",
- "description": "Multiplied by 48"
- },
- "24": {
- "displayName": "*50",
- "headerName": "mul50",
- "description": "Multiplied by 50"
- },
- "25": {
- "displayName": "*52",
- "headerName": "mul52",
- "description": "Multiplied by 52"
- },
- "26": {
- "displayName": "*54",
- "headerName": "mul54",
- "description": "Multiplied by 54"
- },
- "27": {
- "displayName": "*56",
- "headerName": "mul56",
- "description": "Multiplied by 56"
- },
- "28": {
- "displayName": "*58",
- "headerName": "mul58",
- "description": "Multiplied by 58"
- },
- "29": {
- "displayName": "*60",
- "headerName": "mul60",
- "description": "Multiplied by 60"
- },
- "30": {
- "displayName": "*62",
- "headerName": "mul62",
- "description": "Multiplied by 62"
- },
- "31": {
- "displayName": "*64",
- "headerName": "mul64",
- "description": "Multiplied by 64"
- },
- "32": {
- "displayName": "*66",
- "headerName": "mul66",
- "description": "Multiplied by 66"
- },
- "33": {
- "displayName": "*68",
- "headerName": "mul68",
- "description": "Multiplied by 68"
- },
- "34": {
- "displayName": "*70",
- "headerName": "mul70",
- "description": "Multiplied by 70"
- },
- "35": {
- "displayName": "*72",
- "headerName": "mul72",
- "description": "Multiplied by 72"
- },
- "36": {
- "displayName": "*74",
- "headerName": "mul74",
- "description": "Multiplied by 74"
- },
- "37": {
- "displayName": "*76",
- "headerName": "mul76",
- "description": "Multiplied by 76"
- },
- "38": {
- "displayName": "*78",
- "headerName": "mul78",
- "description": "Multiplied by 78"
- },
- "39": {
- "displayName": "*80",
- "headerName": "mul80",
- "description": "Multiplied by 80"
- },
- "40": {
- "displayName": "*82",
- "headerName": "mul82",
- "description": "Multiplied by 82"
- },
- "41": {
- "displayName": "*84",
- "headerName": "mul84",
- "description": "Multiplied by 84"
- },
- "42": {
- "displayName": "*86",
- "headerName": "mul86",
- "description": "Multiplied by 86"
- },
- "43": {
- "displayName": "*88",
- "headerName": "mul88",
- "description": "Multiplied by 88"
- },
- "44": {
- "displayName": "*90",
- "headerName": "mul90",
- "description": "Multiplied by 90"
- },
- "45": {
- "displayName": "*92",
- "headerName": "mul92",
- "description": "Multiplied by 92"
- },
- "46": {
- "displayName": "*94",
- "headerName": "mul94",
- "description": "Multiplied by 94"
- },
- "47": {
- "displayName": "*96",
- "headerName": "mul96",
- "description": "Multiplied by 96"
- },
- "48": {
- "displayName": "*98",
- "headerName": "mul98",
- "description": "Multiplied by 98"
- },
- "49": {
- "displayName": "*100",
- "headerName": "mul100",
- "description": "Multiplied by 100"
- },
- "50": {
- "displayName": "*102",
- "headerName": "mul102",
- "description": "Multiplied by 102"
- },
- "51": {
- "displayName": "*104",
- "headerName": "mul104",
- "description": "Multiplied by 104"
- },
- "52": {
- "displayName": "*106",
- "headerName": "mul106",
- "description": "Multiplied by 106"
- },
- "53": {
- "displayName": "*108",
- "headerName": "mul108",
- "description": "Multiplied by 108"
- },
- "54": {
- "displayName": "*110",
- "headerName": "mul110",
- "description": "Multiplied by 110"
- },
- "55": {
- "displayName": "*112",
- "headerName": "mul112",
- "description": "Multiplied by 112"
- },
- "56": {
- "displayName": "*114",
- "headerName": "mul114",
- "description": "Multiplied by 114"
- },
- "57": {
- "displayName": "*116",
- "headerName": "mul116",
- "description": "Multiplied by 116"
- },
- "58": {
- "displayName": "*118",
- "headerName": "mul118",
- "description": "Multiplied by 118"
- },
- "59": {
- "displayName": "*120",
- "headerName": "mul120",
- "description": "Multiplied by 120"
- },
- "60": {
- "displayName": "*122",
- "headerName": "mul122",
- "description": "Multiplied by 122"
- },
- "61": {
- "displayName": "*124",
- "headerName": "mul124",
- "description": "Multiplied by 124"
- },
- "62": {
- "displayName": "*126",
- "headerName": "mul126",
- "description": "Multiplied by 126"
- },
- "63": {
- "displayName": "*128",
- "headerName": "mul128",
- "description": "Multiplied by 128"
- }
- }
- }
- }
- },
- "q": {
- "description": "PLL Q output divider value",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x3",
- "enumerations": {
- "pllq-enum": {
- "description": "Reference Clock Q Divide Ratio Enumeration",
- "values": {
- "*": {
- "displayName": "n/a",
- "description": "Not supported"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- },
- "3": {
- "displayName": "/8",
- "headerName": "div8",
- "description": "Divided by 8"
- }
- }
- }
- }
- },
- "sel": {
- "description": "PLL select",
- "bitOffset": "16",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "refsel": {
- "description": "PLL reference select",
- "bitOffset": "17",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "bypass": {
- "description": "PLL bypass",
- "bitOffset": "18",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "lock": {
- "description": "PLL lock indicator",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "plloutdiv": {
- "description": "PLL Output Divider",
- "addressOffset": "0x000C"
- }
- }
- },
- "otp": {
- "description": "One-Time Programmable Memory (OTP) Peripheral",
- "baseAddress": "0x10010000",
- "size": "0x1000",
- "registers": {
- "lock": {
- "description": "Programmed-I/O Lock Register",
- "addressOffset": "0x0000"
- },
- "ck": {
- "description": "Device Clock Signal Register",
- "addressOffset": "0x0004"
- },
- "oe": {
- "description": "Device Output-Enable Signal Register",
- "addressOffset": "0x0008"
- },
- "sel": {
- "description": "Device Chip-Select Signal Register",
- "addressOffset": "0x000C"
- },
- "we": {
- "description": "Device Write-Enable Signal Register",
- "addressOffset": "0x0010"
- },
- "mr": {
- "description": "Device Mode Register",
- "addressOffset": "0x0014"
- },
- "mrr": {
- "description": "Read-Voltage Regulator Control Register",
- "addressOffset": "0x0018"
- },
- "mpp": {
- "description": "Write-Voltage Charge Pump Control Register",
- "addressOffset": "0x001C"
- },
- "vrren": {
- "description": "Read-Voltage Enable Register",
- "addressOffset": "0x0020"
- },
- "vppen": {
- "description": "Write-Voltage Enable Register",
- "addressOffset": "0x0024"
- },
- "a": {
- "description": "Device Address Register",
- "addressOffset": "0x0028"
- },
- "d": {
- "description": "Device Data Input Register",
- "addressOffset": "0x002C"
- },
- "q": {
- "description": "Device Data Output Register",
- "addressOffset": "0x0030"
- },
- "rsctrl": {
- "description": "Read Sequencer Control Register",
- "addressOffset": "0x0034",
- "fields": {
- "scale": {
- "description": "OTP timescale",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "tas": {
- "description": "Address setup time",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "trp": {
- "description": "Read pulse time",
- "bitOffset": "4",
- "bitWidth": "1"
- },
- "tracc": {
- "description": "Read access time",
- "bitOffset": "5",
- "bitWidth": "1"
- }
- }
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x10012000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "8"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "9"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "10"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "11"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "12"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "13"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "14"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "15"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "16"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "17"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "18"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "19"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "20"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "21"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "22"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "23"
- },
- "gpio16": {
- "description": "GPIO16 Interrupt",
- "value": "24"
- },
- "gpio17": {
- "description": "GPIO17 Interrupt",
- "value": "25"
- },
- "gpio18": {
- "description": "GPIO18 Interrupt",
- "value": "26"
- },
- "gpio19": {
- "description": "GPIO19 Interrupt",
- "value": "27"
- },
- "gpio20": {
- "description": "GPIO20 Interrupt",
- "value": "28"
- },
- "gpio21": {
- "description": "GPIO21 Interrupt",
- "value": "29"
- },
- "gpio22": {
- "description": "GPIO22 Interrupt",
- "value": "30"
- },
- "gpio23": {
- "description": "GPIO23 Interrupt",
- "value": "31"
- },
- "gpio24": {
- "description": "GPIO24 Interrupt",
- "value": "32"
- },
- "gpio25": {
- "description": "GPIO25 Interrupt",
- "value": "33"
- },
- "gpio26": {
- "description": "GPIO26 Interrupt",
- "value": "34"
- },
- "gpio27": {
- "description": "GPIO27 Interrupt",
- "value": "35"
- },
- "gpio28": {
- "description": "GPIO28 Interrupt",
- "value": "36"
- },
- "gpio29": {
- "description": "GPIO29 Interrupt",
- "value": "37"
- },
- "gpio30": {
- "description": "GPIO30 Interrupt",
- "value": "38"
- },
- "gpio31": {
- "description": "GPIO31 Interrupt",
- "value": "39"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x10013000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "3"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x10014000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "5"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10015000",
- "size": "0x1000",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "40"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "41"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "42"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "43"
- }
- }
- },
- "uart1": {
- "baseAddress": "0x10023000",
- "derivedFrom": "uart0",
- "groupName": "uart",
- "interrupts": {
- "uart1": {
- "description": "UART1 Interrupt",
- "value": "4"
- }
- }
- },
- "spi1": {
- "baseAddress": "0x10024000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi1": {
- "description": "SPI1 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm1": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10025000",
- "groupName": "pwm",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "pwm1cmp0": {
- "description": "PWM1 Compare 0 Interrupt",
- "value": "44"
- },
- "pwm1cmp1": {
- "description": "PWM1 Compare 1 Interrupt",
- "value": "45"
- },
- "pwm1cmp2": {
- "description": "PWM1 Compare 2 Interrupt",
- "value": "46"
- },
- "pwm1cmp3": {
- "description": "PWM1 Compare 3 Interrupt",
- "value": "47"
- }
- }
- },
- "spi2": {
- "baseAddress": "0x10034000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi2": {
- "description": "SPI2 Interrupt",
- "value": "7"
- }
- }
- },
- "pwm2": {
- "baseAddress": "0x10035000",
- "derivedFrom": "pwm1",
- "groupName": "pwm",
- "interrupts": {
- "pwm2cmp0": {
- "description": "PWM2 Compare 0 Interrupt",
- "value": "48"
- },
- "pwm2cmp1": {
- "description": "PWM2 Compare 1 Interrupt",
- "value": "49"
- },
- "pwm2cmp2": {
- "description": "PWM2 Compare 2 Interrupt",
- "value": "50"
- },
- "pwm2cmp3": {
- "description": "PWM2 Compare 3 Interrupt",
- "value": "51"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/HiFive1/hello/hello OpenOCD.launch b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch
deleted file mode 100644
index 55bd731..0000000
--- a/FreedomStudio/HiFive1/hello/hello OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
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diff --git a/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg
deleted file mode 100644
index b0a8e26..0000000
--- a/FreedomStudio/HiFive1/hello/sifive-freedom-e300-hifive1.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
- #Wait for the reset stretcher
- #It will work without this, but
- #will incur lots of delays for later commands.
- sleep 1500
-}
-halt
-flash protect 0 64 last off
diff --git a/FreedomStudio/HiFive1/led_fade/.cproject b/FreedomStudio/HiFive1/led_fade/.cproject
deleted file mode 100644
index e0d1e09..0000000
--- a/FreedomStudio/HiFive1/led_fade/.cproject
+++ /dev/null
@@ -1,210 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/led_fade/.gitignore b/FreedomStudio/HiFive1/led_fade/.gitignore
deleted file mode 100644
index 3df573f..0000000
--- a/FreedomStudio/HiFive1/led_fade/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/FreedomStudio/HiFive1/led_fade/.project b/FreedomStudio/HiFive1/led_fade/.project
deleted file mode 100644
index f915b0d..0000000
--- a/FreedomStudio/HiFive1/led_fade/.project
+++ /dev/null
@@ -1,348 +0,0 @@
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- <link>
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diff --git a/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json b/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json
deleted file mode 100644
index 1722e54..0000000
--- a/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json
+++ /dev/null
@@ -1,2325 +0,0 @@
-{
- "schemaVersion": "0.2.4",
- "contentVersion": "0.2.0",
- "headerVersion": "0.2.0",
- "device": {
- "fe310": {
- "displayName": "Freedom E310-G000",
- "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
- "supplier": {
- "name": "sifive",
- "id": "1",
- "displayName": "SiFive",
- "fullName": "SiFive, Inc.",
- "contact": "info@sifive.com"
- },
- "busWidth": "32",
- "resetMask": "all",
- "resetValue": "0x00000000",
- "access": "rw",
- "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
- "headerTypePrefix": "sifive_fe310_",
- "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
- "headerInterruptEnumPrefix": "riscv_interrupts_global_",
- "revision": "r0p0",
- "numInterrupts": "51",
- "priorityBits": "3",
- "regWidth": "32",
- "cores": {
- "e31": {
- "harts": "1",
- "isa": "RV32IMAC",
- "isaVersion": "2.2",
- "mpu": "pmp",
- "mmu": "none",
- "localInterrupts": {
- "machine_software": {
- "description": "Machine Software Interrupt",
- "value": "3"
- },
- "machine_timer": {
- "description": "Machine Timer Interrupt",
- "value": "7"
- },
- "machine_ext": {
- "description": "Machine External Interrupt",
- "value": "11"
- }
- },
- "numLocalInterrupts": "0"
- }
- },
- "peripherals": {
- "clint": {
- "description": "Core Complex Local Interruptor (CLINT) Peripheral",
- "baseAddress": "0x02000000",
- "size": "0x10000",
- "registers": {
- "msip": {
- "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
- "addressOffset": "0x0000",
- "arraySize": "1"
- }
- },
- "clusters": {
- "mtimecmp": {
- "description": "Machine Time Compare Registers per Hart",
- "addressOffset": "0x4000",
- "arraySize": "1",
- "registers": {
- "low": {
- "description": "Machine Compare Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Compare Register High",
- "addressOffset": "0x0004"
- }
- }
- },
- "mtime": {
- "description": "Machine Time Register",
- "addressOffset": "0xBFF8",
- "access": "r",
- "registers": {
- "low": {
- "description": "Machine Time Register Low",
- "addressOffset": "0x0000"
- },
- "high": {
- "description": "Machine Time Register High",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- },
- "plic": {
- "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
- "baseAddress": "0x0C000000",
- "size": "0x4000000",
- "registers": {
- "priorities": {
- "arraySize": "52",
- "description": "Interrupt Priorities Registers; 0 is reserved.",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority for a given global interrupt",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "pendings": {
- "arraySize": "2",
- "description": "Interrupt Pending Bits Registers",
- "addressOffset": "0x1000",
- "access": "r"
- }
- },
- "clusters": {
- "enablestarget0": {
- "description": "Hart 0 Interrupt Enable Bits",
- "addressOffset": "0x00002000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-mode Interrupt Enable Bits",
- "registers": {
- "enables": {
- "arraySize": "2",
- "description": "Interrupt Enable Bits Registers",
- "addressOffset": "0x0000"
- }
- }
- }
- }
- },
- "target0": {
- "description": "Hart 0 Interrupt Thresholds",
- "addressOffset": "0x00200000",
- "clusters": {
- "m": {
- "addressOffset": "0x0000",
- "description": "Hart 0 M-Mode Interrupt Threshold",
- "registers": {
- "threshold": {
- "description": "The Priority Threshold Register",
- "addressOffset": "0x0000",
- "fields": {
- "value": {
- "description": "The priority threshold value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "claimcomplete": {
- "description": "The Interrupt Claim/Completion Register",
- "addressOffset": "0x0004"
- }
- }
- }
- }
- }
- }
- },
- "wdog": {
- "description": "Watchdog Timer (WDT), part of Always-On Domain",
- "baseAddress": "0x10000000",
- "size": "0x0040",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Watchdog Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "Watchdog counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "rsten": {
- "description": "Watchdog full reset enable",
- "bitOffset": "8",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "zerocmp": {
- "description": "Watchdog zero on comparator",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Watchdog enable counter always",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "encoreawake": {
- "description": "Watchdog counter only when awake",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "Watchdog interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Watchdog Count Register",
- "addressOffset": "0x0008"
- },
- "scale": {
- "description": "Watchdog Scale Register",
- "addressOffset": "0x0010",
- "fields": {
- "value": {
- "description": "Watchdog scale value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "feed": {
- "description": "Watchdog Feed Address Register",
- "addressOffset": "0x0018"
- },
- "key": {
- "description": "Watchdog Key Register",
- "addressOffset": "0x001C"
- },
- "cmp": {
- "description": "Watchdog Compare Register",
- "addressOffset": "0x0020",
- "fields": {
- "value": {
- "description": "Watchdog compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "wdogcmp": {
- "description": "Watchdog Compare Interrupt",
- "value": "1"
- }
- }
- },
- "rtc": {
- "description": "Real-Time Clock (RTC), part of Always-On Domain",
- "baseAddress": "0x10000040",
- "size": "0x0030",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "RTC Configuration Register",
- "addressOffset": "0x0000",
- "fields": {
- "scale": {
- "description": "RTC clock rate scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "enalways": {
- "description": "RTC counter enable",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmpip": {
- "description": "RTC comparator interrupt pending",
- "bitOffset": "28",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "low": {
- "description": "RTC Counter Register Low",
- "addressOffset": "0x0008"
- },
- "high": {
- "description": "RTC Counter Register High",
- "addressOffset": "0x000C",
- "fields": {
- "value": {
- "description": "RTC counter register, high bits",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "scale": {
- "description": "RTC Scale Register",
- "addressOffset": "0x0010"
- },
- "cmp": {
- "description": "RTC Compare Register",
- "addressOffset": "0x0020"
- }
- },
- "interrupts": {
- "rtccmp": {
- "description": "RTC Compare Interrupt",
- "value": "2"
- }
- }
- },
- "pmu": {
- "description": "Power-Management Unit (PMU), part of Always-On Domain",
- "baseAddress": "0x10000100",
- "size": "0x0050",
- "resetMask": "none",
- "registers": {
- "wakeupi": {
- "description": "Wakeup program instruction Registers",
- "addressOffset": "0x0000",
- "arraySize": "8"
- },
- "sleepi": {
- "description": "Sleep Program Instruction Registers",
- "addressOffset": "0x0020",
- "arraySize": "8"
- },
- "ie": {
- "description": "PMU Interrupt Enables Register",
- "addressOffset": "0x0040",
- "fields": {
- "rtc": {
- "description": "RTC Comparator active",
- "bitOffset": "1",
- "bitWidth": "1"
- },
- "dwakeup": {
- "description": "dwakeup_n pin active",
- "bitOffset": "2",
- "bitWidth": "1"
- }
- }
- },
- "cause": {
- "description": "PMU Wakeup Cause Register",
- "addressOffset": "0x0044",
- "fields": {
- "wakeupcause": {
- "description": "Wakeup cause",
- "bitOffset": "0",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "wakeupcause-enum": {
- "description": "Wakeup Cause Values Enumeration",
- "values": {
- "0": {
- "displayName": "reset",
- "description": "Reset Wakeup"
- },
- "1": {
- "displayName": "rtc",
- "description": "RTC Wakeup"
- },
- "2": {
- "displayName": "dwakeup",
- "description": "Digital input Wakeup"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- },
- "resetcause": {
- "description": "Reset cause",
- "bitOffset": "8",
- "bitWidth": "2",
- "access": "r",
- "enumerations": {
- "resetcause-enum": {
- "description": "Reset Cause Values Enumeration",
- "values": {
- "1": {
- "displayName": "external",
- "description": "External reset"
- },
- "2": {
- "displayName": "watchdog",
- "description": "Watchdog timer reset"
- },
- "*": {
- "displayName": "undefined"
- }
- }
- }
- }
- }
- }
- },
- "sleep": {
- "description": "PMU Initiate Sleep Sequence Register",
- "addressOffset": "0x0048"
- },
- "key": {
- "description": "PMU Key Register",
- "addressOffset": "0x004C"
- }
- }
- },
- "aon": {
- "description": "Always-On (AON) Domain",
- "baseAddress": "0x10000070",
- "size": "0x0090",
- "resetMask": "none",
- "registers": {
- "lfrosccfg": {
- "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "LFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "LFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "LFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "LFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "backup": {
- "description": "Backup Registers",
- "addressOffset": "0x0010",
- "arraySize": "32"
- }
- }
- },
- "prci": {
- "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
- "baseAddress": "0x10008000",
- "size": "0x8000",
- "registers": {
- "hfrosccfg": {
- "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
- "addressOffset": "0x0000",
- "fields": {
- "div": {
- "description": "HFROSC divider",
- "bitOffset": "0",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x04"
- },
- "trim": {
- "description": "HFROSC trim value",
- "bitOffset": "16",
- "bitWidth": "5",
- "resetMask": "all",
- "resetValue": "0x10"
- },
- "en": {
- "description": "HFROSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFROSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "hfxosccfg": {
- "description": "External 16 MHz Crystal Oscillator Register",
- "addressOffset": "0x0004",
- "fields": {
- "en": {
- "description": "HFXOSC enable",
- "bitOffset": "30",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "rdy": {
- "description": "HFXOSC ready",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "pllcfg": {
- "description": "Internal High-Frequency PLL (HFPLL) Register",
- "addressOffset": "0x0008",
- "fields": {
- "r": {
- "description": "PLL R input divider value",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "pllr-enum": {
- "description": "Reference Clock R Divide Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "/1",
- "headerName": "div1",
- "description": "Unchanged"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/3",
- "headerName": "div3",
- "description": "Divided by 3"
- },
- "3": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- }
- }
- }
- }
- },
- "f": {
- "description": "PLL F multiplier value",
- "bitOffset": "4",
- "bitWidth": "6",
- "resetMask": "all",
- "resetValue": "0x1F",
- "enumerations": {
- "pllf-enum": {
- "description": "Reference Clock F Multiplier Ratio Enumeration",
- "values": {
- "0": {
- "displayName": "*2",
- "headerName": "mul2",
- "description": "Multiplied by 2"
- },
- "1": {
- "displayName": "*4",
- "headerName": "mul4",
- "description": "Multiplied by 4"
- },
- "2": {
- "displayName": "*6",
- "headerName": "mul6",
- "description": "Multiplied by 6"
- },
- "3": {
- "displayName": "*8",
- "headerName": "mul8",
- "description": "Multiplied by 8"
- },
- "4": {
- "displayName": "*10",
- "headerName": "mul10",
- "description": "Multiplied by 10"
- },
- "5": {
- "displayName": "*12",
- "headerName": "mul12",
- "description": "Multiplied by 12"
- },
- "6": {
- "displayName": "*14",
- "headerName": "mul14",
- "description": "Multiplied by 14"
- },
- "7": {
- "displayName": "*16",
- "headerName": "mul16",
- "description": "Multiplied by 16"
- },
- "8": {
- "displayName": "*18",
- "headerName": "mul18",
- "description": "Multiplied by 18"
- },
- "9": {
- "displayName": "*20",
- "headerName": "mul20",
- "description": "Multiplied by 20"
- },
- "10": {
- "displayName": "*22",
- "headerName": "mul22",
- "description": "Multiplied by 22"
- },
- "11": {
- "displayName": "*24",
- "headerName": "mul24",
- "description": "Multiplied by 24"
- },
- "12": {
- "displayName": "*26",
- "headerName": "mul26",
- "description": "Multiplied by 26"
- },
- "13": {
- "displayName": "*28",
- "headerName": "mul28",
- "description": "Multiplied by 28"
- },
- "14": {
- "displayName": "*30",
- "headerName": "mul30",
- "description": "Multiplied by 30"
- },
- "15": {
- "displayName": "*32",
- "headerName": "mul32",
- "description": "Multiplied by 32"
- },
- "16": {
- "displayName": "*34",
- "headerName": "mul34",
- "description": "Multiplied by 34"
- },
- "17": {
- "displayName": "*36",
- "headerName": "mul36",
- "description": "Multiplied by 36"
- },
- "18": {
- "displayName": "*38",
- "headerName": "mul38",
- "description": "Multiplied by 38"
- },
- "19": {
- "displayName": "*40",
- "headerName": "mul40",
- "description": "Multiplied by 40"
- },
- "20": {
- "displayName": "*42",
- "headerName": "mul42",
- "description": "Multiplied by 42"
- },
- "21": {
- "displayName": "*44",
- "headerName": "mul44",
- "description": "Multiplied by 44"
- },
- "22": {
- "displayName": "*46",
- "headerName": "mul46",
- "description": "Multiplied by 46"
- },
- "23": {
- "displayName": "*48",
- "headerName": "mul48",
- "description": "Multiplied by 48"
- },
- "24": {
- "displayName": "*50",
- "headerName": "mul50",
- "description": "Multiplied by 50"
- },
- "25": {
- "displayName": "*52",
- "headerName": "mul52",
- "description": "Multiplied by 52"
- },
- "26": {
- "displayName": "*54",
- "headerName": "mul54",
- "description": "Multiplied by 54"
- },
- "27": {
- "displayName": "*56",
- "headerName": "mul56",
- "description": "Multiplied by 56"
- },
- "28": {
- "displayName": "*58",
- "headerName": "mul58",
- "description": "Multiplied by 58"
- },
- "29": {
- "displayName": "*60",
- "headerName": "mul60",
- "description": "Multiplied by 60"
- },
- "30": {
- "displayName": "*62",
- "headerName": "mul62",
- "description": "Multiplied by 62"
- },
- "31": {
- "displayName": "*64",
- "headerName": "mul64",
- "description": "Multiplied by 64"
- },
- "32": {
- "displayName": "*66",
- "headerName": "mul66",
- "description": "Multiplied by 66"
- },
- "33": {
- "displayName": "*68",
- "headerName": "mul68",
- "description": "Multiplied by 68"
- },
- "34": {
- "displayName": "*70",
- "headerName": "mul70",
- "description": "Multiplied by 70"
- },
- "35": {
- "displayName": "*72",
- "headerName": "mul72",
- "description": "Multiplied by 72"
- },
- "36": {
- "displayName": "*74",
- "headerName": "mul74",
- "description": "Multiplied by 74"
- },
- "37": {
- "displayName": "*76",
- "headerName": "mul76",
- "description": "Multiplied by 76"
- },
- "38": {
- "displayName": "*78",
- "headerName": "mul78",
- "description": "Multiplied by 78"
- },
- "39": {
- "displayName": "*80",
- "headerName": "mul80",
- "description": "Multiplied by 80"
- },
- "40": {
- "displayName": "*82",
- "headerName": "mul82",
- "description": "Multiplied by 82"
- },
- "41": {
- "displayName": "*84",
- "headerName": "mul84",
- "description": "Multiplied by 84"
- },
- "42": {
- "displayName": "*86",
- "headerName": "mul86",
- "description": "Multiplied by 86"
- },
- "43": {
- "displayName": "*88",
- "headerName": "mul88",
- "description": "Multiplied by 88"
- },
- "44": {
- "displayName": "*90",
- "headerName": "mul90",
- "description": "Multiplied by 90"
- },
- "45": {
- "displayName": "*92",
- "headerName": "mul92",
- "description": "Multiplied by 92"
- },
- "46": {
- "displayName": "*94",
- "headerName": "mul94",
- "description": "Multiplied by 94"
- },
- "47": {
- "displayName": "*96",
- "headerName": "mul96",
- "description": "Multiplied by 96"
- },
- "48": {
- "displayName": "*98",
- "headerName": "mul98",
- "description": "Multiplied by 98"
- },
- "49": {
- "displayName": "*100",
- "headerName": "mul100",
- "description": "Multiplied by 100"
- },
- "50": {
- "displayName": "*102",
- "headerName": "mul102",
- "description": "Multiplied by 102"
- },
- "51": {
- "displayName": "*104",
- "headerName": "mul104",
- "description": "Multiplied by 104"
- },
- "52": {
- "displayName": "*106",
- "headerName": "mul106",
- "description": "Multiplied by 106"
- },
- "53": {
- "displayName": "*108",
- "headerName": "mul108",
- "description": "Multiplied by 108"
- },
- "54": {
- "displayName": "*110",
- "headerName": "mul110",
- "description": "Multiplied by 110"
- },
- "55": {
- "displayName": "*112",
- "headerName": "mul112",
- "description": "Multiplied by 112"
- },
- "56": {
- "displayName": "*114",
- "headerName": "mul114",
- "description": "Multiplied by 114"
- },
- "57": {
- "displayName": "*116",
- "headerName": "mul116",
- "description": "Multiplied by 116"
- },
- "58": {
- "displayName": "*118",
- "headerName": "mul118",
- "description": "Multiplied by 118"
- },
- "59": {
- "displayName": "*120",
- "headerName": "mul120",
- "description": "Multiplied by 120"
- },
- "60": {
- "displayName": "*122",
- "headerName": "mul122",
- "description": "Multiplied by 122"
- },
- "61": {
- "displayName": "*124",
- "headerName": "mul124",
- "description": "Multiplied by 124"
- },
- "62": {
- "displayName": "*126",
- "headerName": "mul126",
- "description": "Multiplied by 126"
- },
- "63": {
- "displayName": "*128",
- "headerName": "mul128",
- "description": "Multiplied by 128"
- }
- }
- }
- }
- },
- "q": {
- "description": "PLL Q output divider value",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x3",
- "enumerations": {
- "pllq-enum": {
- "description": "Reference Clock Q Divide Ratio Enumeration",
- "values": {
- "*": {
- "displayName": "n/a",
- "description": "Not supported"
- },
- "1": {
- "displayName": "/2",
- "headerName": "div2",
- "description": "Divided by 2"
- },
- "2": {
- "displayName": "/4",
- "headerName": "div4",
- "description": "Divided by 4"
- },
- "3": {
- "displayName": "/8",
- "headerName": "div8",
- "description": "Divided by 8"
- }
- }
- }
- }
- },
- "sel": {
- "description": "PLL select",
- "bitOffset": "16",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "refsel": {
- "description": "PLL reference select",
- "bitOffset": "17",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "bypass": {
- "description": "PLL bypass",
- "bitOffset": "18",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "lock": {
- "description": "PLL lock indicator",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "plloutdiv": {
- "description": "PLL Output Divider",
- "addressOffset": "0x000C"
- }
- }
- },
- "otp": {
- "description": "One-Time Programmable Memory (OTP) Peripheral",
- "baseAddress": "0x10010000",
- "size": "0x1000",
- "registers": {
- "lock": {
- "description": "Programmed-I/O Lock Register",
- "addressOffset": "0x0000"
- },
- "ck": {
- "description": "Device Clock Signal Register",
- "addressOffset": "0x0004"
- },
- "oe": {
- "description": "Device Output-Enable Signal Register",
- "addressOffset": "0x0008"
- },
- "sel": {
- "description": "Device Chip-Select Signal Register",
- "addressOffset": "0x000C"
- },
- "we": {
- "description": "Device Write-Enable Signal Register",
- "addressOffset": "0x0010"
- },
- "mr": {
- "description": "Device Mode Register",
- "addressOffset": "0x0014"
- },
- "mrr": {
- "description": "Read-Voltage Regulator Control Register",
- "addressOffset": "0x0018"
- },
- "mpp": {
- "description": "Write-Voltage Charge Pump Control Register",
- "addressOffset": "0x001C"
- },
- "vrren": {
- "description": "Read-Voltage Enable Register",
- "addressOffset": "0x0020"
- },
- "vppen": {
- "description": "Write-Voltage Enable Register",
- "addressOffset": "0x0024"
- },
- "a": {
- "description": "Device Address Register",
- "addressOffset": "0x0028"
- },
- "d": {
- "description": "Device Data Input Register",
- "addressOffset": "0x002C"
- },
- "q": {
- "description": "Device Data Output Register",
- "addressOffset": "0x0030"
- },
- "rsctrl": {
- "description": "Read Sequencer Control Register",
- "addressOffset": "0x0034",
- "fields": {
- "scale": {
- "description": "OTP timescale",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "tas": {
- "description": "Address setup time",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "trp": {
- "description": "Read pulse time",
- "bitOffset": "4",
- "bitWidth": "1"
- },
- "tracc": {
- "description": "Read access time",
- "bitOffset": "5",
- "bitWidth": "1"
- }
- }
- }
- }
- },
- "gpio": {
- "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
- "baseAddress": "0x10012000",
- "size": "0x1000",
- "registers": {
- "value": {
- "description": "Pin Value Register",
- "addressOffset": "0x000",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "inputen": {
- "description": "Pin Input Enable Register",
- "addressOffset": "0x004",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Input Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outputen": {
- "description": "Pin Output Enable Register",
- "addressOffset": "0x008",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Output Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "port": {
- "description": "Output Port Value Register",
- "addressOffset": "0x00C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output Port Value Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "pue": {
- "description": "Internal Pull-up Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Internal Pull-up Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "ds": {
- "description": "Pin Drive Strength Register",
- "addressOffset": "0x014",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Pin Drive Strength Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseie": {
- "description": "Rise Interrupt Enable Register",
- "addressOffset": "0x018",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "riseip": {
- "description": "Rise Interrupt Pending Register",
- "addressOffset": "0x01C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Rise Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallie": {
- "description": "Fall Interrupt Enable Register",
- "addressOffset": "0x020",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "fallip": {
- "description": "Fall Interrupt Pending Register",
- "addressOffset": "0x024",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Fall Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highie": {
- "description": "High Interrupt Enable Register",
- "addressOffset": "0x028",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "highip": {
- "description": "High Interrupt Pending Register",
- "addressOffset": "0x02C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "High Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowie": {
- "description": "Low Interrupt Enable Register",
- "addressOffset": "0x030",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "lowip": {
- "description": "Low Interrupt Pending Register",
- "addressOffset": "0x034",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Low Interrupt Pending Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofen": {
- "description": "HW I/O Function Enable Register",
- "addressOffset": "0x038",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Enable Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "iofsel": {
- "description": "HW I/O Function Select Register",
- "addressOffset": "0x03C",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "HW I/O Function Select Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- },
- "outxor": {
- "description": "Output XOR (invert) Register",
- "addressOffset": "0x040",
- "fields": {
- "bit": {
- "repeatGenerator": "0-31",
- "description": "Output XOR Bit Field",
- "bitOffset": "0",
- "bitWidth": "1",
- "headerName": ""
- }
- }
- }
- },
- "interrupts": {
- "gpio0": {
- "description": "GPIO0 Interrupt",
- "value": "8"
- },
- "gpio1": {
- "description": "GPIO1 Interrupt",
- "value": "9"
- },
- "gpio2": {
- "description": "GPIO2 Interrupt",
- "value": "10"
- },
- "gpio3": {
- "description": "GPIO3 Interrupt",
- "value": "11"
- },
- "gpio4": {
- "description": "GPIO4 Interrupt",
- "value": "12"
- },
- "gpio5": {
- "description": "GPIO5 Interrupt",
- "value": "13"
- },
- "gpio6": {
- "description": "GPIO6 Interrupt",
- "value": "14"
- },
- "gpio7": {
- "description": "GPIO7 Interrupt",
- "value": "15"
- },
- "gpio8": {
- "description": "GPIO8 Interrupt",
- "value": "16"
- },
- "gpio9": {
- "description": "GPIO9 Interrupt",
- "value": "17"
- },
- "gpio10": {
- "description": "GPIO10 Interrupt",
- "value": "18"
- },
- "gpio11": {
- "description": "GPIO11 Interrupt",
- "value": "19"
- },
- "gpio12": {
- "description": "GPIO12 Interrupt",
- "value": "20"
- },
- "gpio13": {
- "description": "GPIO13 Interrupt",
- "value": "21"
- },
- "gpio14": {
- "description": "GPIO14 Interrupt",
- "value": "22"
- },
- "gpio15": {
- "description": "GPIO15 Interrupt",
- "value": "23"
- },
- "gpio16": {
- "description": "GPIO16 Interrupt",
- "value": "24"
- },
- "gpio17": {
- "description": "GPIO17 Interrupt",
- "value": "25"
- },
- "gpio18": {
- "description": "GPIO18 Interrupt",
- "value": "26"
- },
- "gpio19": {
- "description": "GPIO19 Interrupt",
- "value": "27"
- },
- "gpio20": {
- "description": "GPIO20 Interrupt",
- "value": "28"
- },
- "gpio21": {
- "description": "GPIO21 Interrupt",
- "value": "29"
- },
- "gpio22": {
- "description": "GPIO22 Interrupt",
- "value": "30"
- },
- "gpio23": {
- "description": "GPIO23 Interrupt",
- "value": "31"
- },
- "gpio24": {
- "description": "GPIO24 Interrupt",
- "value": "32"
- },
- "gpio25": {
- "description": "GPIO25 Interrupt",
- "value": "33"
- },
- "gpio26": {
- "description": "GPIO26 Interrupt",
- "value": "34"
- },
- "gpio27": {
- "description": "GPIO27 Interrupt",
- "value": "35"
- },
- "gpio28": {
- "description": "GPIO28 Interrupt",
- "value": "36"
- },
- "gpio29": {
- "description": "GPIO29 Interrupt",
- "value": "37"
- },
- "gpio30": {
- "description": "GPIO30 Interrupt",
- "value": "38"
- },
- "gpio31": {
- "description": "GPIO31 Interrupt",
- "value": "39"
- }
- }
- },
- "uart0": {
- "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
- "baseAddress": "0x10013000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "uart",
- "registers": {
- "txdata": {
- "description": "Transmit Data Register",
- "addressOffset": "0x000",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "full": {
- "description": "Transmit FIFO full",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "rxdata": {
- "description": "Receive Data Register",
- "addressOffset": "0x004",
- "resetMask": "none",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8",
- "access": "r"
- },
- "empty": {
- "description": "Receive FIFO empty",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txctrl": {
- "description": "Transmit Control Register ",
- "addressOffset": "0x008",
- "fields": {
- "txen": {
- "description": "Transmit enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "nstop": {
- "description": "Number of stop bits",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "txcnt": {
- "description": "Transmit watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "rxctrl": {
- "description": "Receive Control Register",
- "addressOffset": "0x00C",
- "fields": {
- "rxen": {
- "description": "Receive enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxcnt": {
- "description": "Receive watermark level",
- "bitOffset": "16",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x010",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark interrupt enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x014",
- "access": "r",
- "fields": {
- "txwm": {
- "description": "Transmit watermark interrupt pending",
- "bitOffset": "0",
- "bitWidth": "1"
- },
- "rxwm": {
- "description": "Receive watermark interrupt pending",
- "bitOffset": "1",
- "bitWidth": "1"
- }
- }
- },
- "div": {
- "description": "Baud Rate Divisor Register",
- "addressOffset": "0x018",
- "fields": {
- "value": {
- "description": "Baud rate divisor",
- "bitOffset": "0",
- "bitWidth": "16",
- "resetMask": "all",
- "resetValue": "0x0000FFFF"
- }
- }
- }
- },
- "interrupts": {
- "uart0": {
- "description": "UART0 Interrupt",
- "value": "3"
- }
- }
- },
- "spi0": {
- "description": "Serial Peripheral Interface (SPI) Peripheral",
- "baseAddress": "0x10014000",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "spi",
- "registers": {
- "sckdiv": {
- "description": "Serial clock divisor Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Divisor for serial clock",
- "bitOffset": "0",
- "bitWidth": "12",
- "resetMask": "all",
- "resetValue": "0x003"
- }
- }
- },
- "sckmode": {
- "description": "Serial Clock Mode Register",
- "addressOffset": "0x004",
- "fields": {
- "pha": {
- "description": "Serial clock phase",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "pol": {
- "description": "Serial clock polarity",
- "bitOffset": "1",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "csid": {
- "description": "Chip Select ID Register",
- "addressOffset": "0x010",
- "resetMask": "all",
- "resetValue": "0x00000000"
- },
- "csdef": {
- "description": "Chip Select Default Register",
- "addressOffset": "0x014",
- "resetMask": "all",
- "resetValue": "0x00000001"
- },
- "csmode": {
- "description": "Chip Select Mode Register",
- "addressOffset": "0x018",
- "fields": {
- "mode": {
- "description": "Chip select mode",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "csmode-enum": {
- "description": "Chip Select Modes Enumeration",
- "values": {
- "0": {
- "displayName": "auto",
- "description": "Assert/de-assert CS at the beginning/end of each frame"
- },
- "*": {
- "displayName": "reserved"
- },
- "2": {
- "displayName": "hold",
- "description": "Keep CS continuously asserted after the initial frame"
- },
- "3": {
- "displayName": "off",
- "description": "Disable hardware control of the CS pin"
- }
- }
- }
- }
- }
- }
- },
- "delay0": {
- "description": "Delay Control 0 Register",
- "addressOffset": "0x028",
- "fields": {
- "cssck": {
- "description": "CS to SCK Delay",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "sckcs": {
- "description": "SCK to CS Delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "delay1": {
- "description": "Delay Control 1 Register",
- "addressOffset": "0x02C",
- "fields": {
- "intercs": {
- "description": "Minimum CS inactive time",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- },
- "interxfr": {
- "description": "Maximum interframe delay",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x01"
- }
- }
- },
- "fmt": {
- "description": "Frame Format Register",
- "addressOffset": "0x040",
- "fields": {
- "proto": {
- "description": "SPI Protocol",
- "bitOffset": "0",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "proto-enum": {
- "description": "SPI Protocol Enumeration",
- "values": {
- "0": {
- "displayName": "single",
- "description": "DQ0 (MOSI), DQ1 (MISO)"
- },
- "1": {
- "displayName": "dual",
- "description": "DQ0, DQ1"
- },
- "2": {
- "displayName": "quad",
- "description": "DQ0, DQ1, DQ2, DQ3"
- },
- "*": {
- "displayName": "reserved"
- }
- }
- }
- }
- },
- "endian": {
- "description": "SPI endianness",
- "bitOffset": "2",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0",
- "enumerations": {
- "endian-enum": {
- "description": "SPI Endianness Enumeration",
- "values": {
- "0": {
- "displayName": "msb",
- "description": "Transmit most-significant bit (MSB) first"
- },
- "1": {
- "displayName": "lsb",
- "description": "Transmit least-significant bit (LSB) first"
- }
- }
- }
- }
- },
- "dir": {
- "description": "SPI I/O Direction",
- "bitOffset": "3",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1",
- "enumerations": {
- "dir-enum": {
- "description": "SPI I/O Direction Enumeration",
- "values": {
- "0": {
- "displayName": "rx",
- "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
- },
- "1": {
- "displayName": "tx",
- "description": "The receive FIFO is not populated."
- }
- }
- }
- }
- },
- "len": {
- "description": "Number of bits per frame",
- "bitOffset": "16",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x8"
- }
- }
- },
- "txdata": {
- "description": "Tx FIFO Data Register",
- "addressOffset": "0x048",
- "fields": {
- "data": {
- "description": "Transmit data",
- "bitOffset": "0",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x00"
- },
- "full": {
- "description": "FIFO full flag",
- "bitOffset": "31",
- "bitWidth": "1",
- "access": "r"
- }
- }
- },
- "rxdata": {
- "description": "Rx FIFO Data Register",
- "addressOffset": "0x04C",
- "resetMask": "none",
- "access": "r",
- "fields": {
- "data": {
- "description": "Received data",
- "bitOffset": "0",
- "bitWidth": "8"
- },
- "empty": {
- "description": "FIFO empty flag",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "txmark": {
- "description": "Tx FIFO Watermark Register",
- "addressOffset": "0x050",
- "fields": {
- "value": {
- "description": "Transmit watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "rxmark": {
- "description": "Rx FIFO Watermark Register",
- "addressOffset": "0x054",
- "fields": {
- "value": {
- "description": "Receive watermark",
- "bitOffset": "0",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "fctrl": {
- "description": "Flash Interface Control Register",
- "addressOffset": "0x060",
- "fields": {
- "en": {
- "description": "SPI Flash Mode Select",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- }
- }
- },
- "ffmt": {
- "description": "Flash Instruction Format Register",
- "addressOffset": "0x064",
- "fields": {
- "cmden": {
- "description": "Enable sending of command",
- "bitOffset": "0",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x1"
- },
- "addrlen": {
- "description": "Number of address bytes(0 to 4)",
- "bitOffset": "1",
- "bitWidth": "3",
- "resetMask": "all",
- "resetValue": "0x3"
- },
- "padcnt": {
- "description": "Number of dummy cycles",
- "bitOffset": "4",
- "bitWidth": "4",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdproto": {
- "description": "Protocol for transmitting command",
- "bitOffset": "8",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "addrproto": {
- "description": "Protocol for transmitting address and padding",
- "bitOffset": "10",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "dataproto": {
- "description": "Protocol for receiving data bytes",
- "bitOffset": "12",
- "bitWidth": "2",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmdcode": {
- "description": "Value of command byte",
- "bitOffset": "16",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x03"
- },
- "padcode": {
- "description": "First 8 bits to transmit during dummy cycles",
- "bitOffset": "24",
- "bitWidth": "8",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ie": {
- "description": "Interrupt Enable Register",
- "addressOffset": "0x070",
- "fields": {
- "txwm": {
- "description": "Transmit watermark enable",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "rxwm": {
- "description": "Receive watermark enable",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r",
- "resetMask": "all",
- "resetValue": "0x0"
- }
- }
- },
- "ip": {
- "description": "Interrupt Pending Register",
- "addressOffset": "0x074",
- "fields": {
- "txwm": {
- "description": "Transmit watermark pending",
- "bitOffset": "0",
- "bitWidth": "1",
- "access": "r"
- },
- "rxwm": {
- "description": "Receive watermark pending",
- "bitOffset": "1",
- "bitWidth": "1",
- "access": "r"
- }
- }
- }
- },
- "interrupts": {
- "spi0": {
- "description": "SPI0 Interrupt",
- "value": "5"
- }
- }
- },
- "pwm0": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10015000",
- "size": "0x1000",
- "resetMask": "none",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "8"
- }
- }
- }
- },
- "interrupts": {
- "pwm0cmp0": {
- "description": "PWM0 Compare 0 Interrupt",
- "value": "40"
- },
- "pwm0cmp1": {
- "description": "PWM0 Compare 1 Interrupt",
- "value": "41"
- },
- "pwm0cmp2": {
- "description": "PWM0 Compare 2 Interrupt",
- "value": "42"
- },
- "pwm0cmp3": {
- "description": "PWM0 Compare 3 Interrupt",
- "value": "43"
- }
- }
- },
- "uart1": {
- "baseAddress": "0x10023000",
- "derivedFrom": "uart0",
- "groupName": "uart",
- "interrupts": {
- "uart1": {
- "description": "UART1 Interrupt",
- "value": "4"
- }
- }
- },
- "spi1": {
- "baseAddress": "0x10024000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi1": {
- "description": "SPI1 Interrupt",
- "value": "6"
- }
- }
- },
- "pwm1": {
- "description": "Pulse-Width Modulation (PWM) Peripheral",
- "baseAddress": "0x10025000",
- "groupName": "pwm",
- "size": "0x1000",
- "resetMask": "none",
- "groupName": "pwm",
- "registers": {
- "cfg": {
- "description": "Configuration Register",
- "addressOffset": "0x000",
- "fields": {
- "scale": {
- "description": "Counter scale",
- "bitOffset": "0",
- "bitWidth": "4"
- },
- "sticky": {
- "description": "Sticky - disallow clearing pwmcmpXip bits",
- "bitOffset": "8",
- "bitWidth": "1"
- },
- "zerocmp": {
- "description": "Zero - counter resets to zero after match",
- "bitOffset": "9",
- "bitWidth": "1"
- },
- "deglitch": {
- "description": "Deglitch - latch pwmcmpXip within same cycle",
- "bitOffset": "10",
- "bitWidth": "1"
- },
- "enalways": {
- "description": "Enable always - run continuously",
- "bitOffset": "12",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "enoneshot": {
- "description": "enable one shot - run one cycle",
- "bitOffset": "13",
- "bitWidth": "1",
- "resetMask": "all",
- "resetValue": "0x0"
- },
- "cmp0center": {
- "description": "PWM0 Compare Center",
- "bitOffset": "16",
- "bitWidth": "1"
- },
- "cmp1center": {
- "description": "PWM1 Compare Center",
- "bitOffset": "17",
- "bitWidth": "1"
- },
- "cmp2center": {
- "description": "PWM2 Compare Center",
- "bitOffset": "18",
- "bitWidth": "1"
- },
- "cmp3center": {
- "description": "PWM3 Compare Center",
- "bitOffset": "19",
- "bitWidth": "1"
- },
- "cmp0gang": {
- "description": "PWM0/PWM1 Compare Gang",
- "bitOffset": "24",
- "bitWidth": "1"
- },
- "cmp1gang": {
- "description": "PWM1/PWM2 Compare Gang",
- "bitOffset": "25",
- "bitWidth": "1"
- },
- "cmp2gang": {
- "description": "PWM2/PWM3 Compare Gang",
- "bitOffset": "26",
- "bitWidth": "1"
- },
- "cmp3gang": {
- "description": "PWM3/PWM0 Compare Gang",
- "bitOffset": "27",
- "bitWidth": "1"
- },
- "cmp0ip": {
- "description": "PWM0 Interrupt Pending",
- "bitOffset": "28",
- "bitWidth": "1"
- },
- "cmp1ip": {
- "description": "PWM1 Interrupt Pending",
- "bitOffset": "29",
- "bitWidth": "1"
- },
- "cmp2ip": {
- "description": "PWM2 Interrupt Pending",
- "bitOffset": "30",
- "bitWidth": "1"
- },
- "cmp3ip": {
- "description": "PWM3 Interrupt Pending",
- "bitOffset": "31",
- "bitWidth": "1"
- }
- }
- },
- "count": {
- "description": "Configuration Register",
- "addressOffset": "0x008"
- },
- "scale": {
- "description": "Scale Register",
- "addressOffset": "0x010",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- },
- "cmp": {
- "arraySize": "4",
- "description": "Compare Registers",
- "addressOffset": "0x020",
- "fields": {
- "value": {
- "description": "Compare value",
- "bitOffset": "0",
- "bitWidth": "16"
- }
- }
- }
- },
- "interrupts": {
- "pwm1cmp0": {
- "description": "PWM1 Compare 0 Interrupt",
- "value": "44"
- },
- "pwm1cmp1": {
- "description": "PWM1 Compare 1 Interrupt",
- "value": "45"
- },
- "pwm1cmp2": {
- "description": "PWM1 Compare 2 Interrupt",
- "value": "46"
- },
- "pwm1cmp3": {
- "description": "PWM1 Compare 3 Interrupt",
- "value": "47"
- }
- }
- },
- "spi2": {
- "baseAddress": "0x10034000",
- "derivedFrom": "spi0",
- "groupName": "spi",
- "interrupts": {
- "spi2": {
- "description": "SPI2 Interrupt",
- "value": "7"
- }
- }
- },
- "pwm2": {
- "baseAddress": "0x10035000",
- "derivedFrom": "pwm1",
- "groupName": "pwm",
- "interrupts": {
- "pwm2cmp0": {
- "description": "PWM2 Compare 0 Interrupt",
- "value": "48"
- },
- "pwm2cmp1": {
- "description": "PWM2 Compare 1 Interrupt",
- "value": "49"
- },
- "pwm2cmp2": {
- "description": "PWM2 Compare 2 Interrupt",
- "value": "50"
- },
- "pwm2cmp3": {
- "description": "PWM2 Compare 3 Interrupt",
- "value": "51"
- }
- }
- }
- }
- }
- }
-} \ No newline at end of file
diff --git a/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch b/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch
deleted file mode 100644
index abe9c3e..0000000
--- a/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch
+++ /dev/null
@@ -1,60 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32&#10;set remotetimeout 250"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-freedom-e300-hifive1.cfg"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/led_fade.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="led_fade"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/led_fade"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg b/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg
deleted file mode 100644
index b0a8e26..0000000
--- a/FreedomStudio/HiFive1/led_fade/sifive-freedom-e300-hifive1.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-adapter_khz 10000
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x001b
-ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
-
-#Reset Stretcher logic on FE310 is ~1 second long
-#This doesn't apply if you use
-# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-
-flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
-init
-#reset -- This type of reset is not implemented yet
-if {[ info exists pulse_srst]} {
- ftdi_set_signal nSRST 0
- ftdi_set_signal nSRST z
- #Wait for the reset stretcher
- #It will work without this, but
- #will incur lots of delays for later commands.
- sleep 1500
-}
-halt
-flash protect 0 64 last off