diff options
| -rw-r--r-- | bsp/coreip-e20/README.md | 1 | ||||
| -rw-r--r-- | bsp/coreip-e31-arty/README.md | 6 | ||||
| -rw-r--r-- | bsp/coreip-e31/README.md | 2 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/README.md | 6 | ||||
| -rw-r--r-- | bsp/coreip-s51/README.md | 2 | ||||
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 6 |
6 files changed, 11 insertions, 12 deletions
diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md index 4c9fe1a..f908327 100644 --- a/bsp/coreip-e20/README.md +++ b/bsp/coreip-e20/README.md @@ -4,4 +4,3 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMC core - 4 hardware breakpoints -- Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md index eeb3502..c6558cb 100644 --- a/bsp/coreip-e31-arty/README.md +++ b/bsp/coreip-e31-arty/README.md @@ -1,14 +1,14 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index ebfe371..324369d 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md index be9d317..0290171 100644 --- a/bsp/coreip-s51-arty/README.md +++ b/bsp/coreip-s51-arty/README.md @@ -1,14 +1,14 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index a640a47..60f75bf 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index faca2eb..6311207 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,13 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. -his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS |