diff options
| -rw-r--r-- | bsp/coreip-e31-arty/design.dts | 4 | ||||
| -rw-r--r-- | bsp/coreip-e31/design.dts | 4 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/design.dts | 4 | ||||
| -rw-r--r-- | bsp/coreip-s51/design.dts | 4 |
4 files changed, 16 insertions, 0 deletions
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index 3e12f77..96698e9 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -45,6 +45,10 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts index 3411ccf..f7e9868 100644 --- a/bsp/coreip-e31/design.dts +++ b/bsp/coreip-e31/design.dts @@ -33,6 +33,10 @@ #size-cells = <1>; compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L12: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 71b9ea6..ea349bb 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -45,6 +45,10 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; diff --git a/bsp/coreip-s51/design.dts b/bsp/coreip-s51/design.dts index 000ff94..a1cb9fc 100644 --- a/bsp/coreip-s51/design.dts +++ b/bsp/coreip-s51/design.dts @@ -33,6 +33,10 @@ #size-cells = <2>; compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L12: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; |