diff options
| -rw-r--r-- | bsp/coreip-e20/README.md | 6 | ||||
| -rw-r--r-- | bsp/coreip-e21/README.md | 7 | ||||
| -rw-r--r-- | bsp/coreip-e31-arty/README.md | 14 | ||||
| -rw-r--r-- | bsp/coreip-e31/README.md | 9 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/README.md | 14 | ||||
| -rw-r--r-- | bsp/coreip-s51/README.md | 9 | ||||
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 13 | ||||
| -rw-r--r-- | scripts/libmetal.mk | 2 | ||||
| -rw-r--r-- | scripts/standalone.mk | 6 |
9 files changed, 76 insertions, 4 deletions
diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md new file mode 100644 index 0000000..f908327 --- /dev/null +++ b/bsp/coreip-e20/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMC core +- 4 hardware breakpoints diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md new file mode 100644 index 0000000..a2f1a61 --- /dev/null +++ b/bsp/coreip-e21/README.md @@ -0,0 +1,7 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md new file mode 100644 index 0000000..c6558cb --- /dev/null +++ b/bsp/coreip-e31-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md new file mode 100644 index 0000000..324369d --- /dev/null +++ b/bsp/coreip-e31/README.md @@ -0,0 +1,9 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md new file mode 100644 index 0000000..0290171 --- /dev/null +++ b/bsp/coreip-s51-arty/README.md @@ -0,0 +1,14 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md new file mode 100644 index 0000000..60f75bf --- /dev/null +++ b/bsp/coreip-s51/README.md @@ -0,0 +1,9 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md new file mode 100644 index 0000000..6311207 --- /dev/null +++ b/bsp/sifive-hifive1/README.md @@ -0,0 +1,13 @@ +HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS diff --git a/scripts/libmetal.mk b/scripts/libmetal.mk index 7cdb7c5..ea16632 100644 --- a/scripts/libmetal.mk +++ b/scripts/libmetal.mk @@ -13,7 +13,7 @@ $(BSP_DIR)/build/Makefile: @rm -rf $(dir $@) @mkdir -p $(dir $@) cd $(dir $@) && \ - CFLAGS="-march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany" \ + CFLAGS="-march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany" \ $(abspath $(MEE_SOURCE_PATH)/configure) \ --host=$(CROSS_COMPILE) \ --prefix=$(abspath $(BSP_DIR)/install) \ diff --git a/scripts/standalone.mk b/scripts/standalone.mk index 52926ac..a412710 100644 --- a/scripts/standalone.mk +++ b/scripts/standalone.mk @@ -90,10 +90,10 @@ $(PROGRAM_ELF): \ AR=$(RISCV_AR) \ CC=$(RISCV_GCC) \ CXX=$(RISCV_GXX) \ - CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ - CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ LDFLAGS="-nostartfiles -nostdlib -L$(sort $(dir $(abspath $(filter %.a,$^)))) -T$(abspath $(filter %.lds,$^))" \ - LDLIBS="-Wl,--start-group -lc -lgcc -lmetal -lmetal-gloss -Wl,--end-group" + LDLIBS="-Wl,--gc-sections -Wl,--start-group -lc -lgcc -lmetal -lmetal-gloss -Wl,--end-group" touch -c $@ .PHONY: clean-software |