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-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/.cproject15
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/.project154
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch2
-rw-r--r--FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.cproject213
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.gitignore (renamed from FreedomStudio/E51FPGA/wrap-E51FPGA/.gitignore)0
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.project378
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml25
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch62
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg31
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/.cproject15
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/.project154
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch (renamed from FreedomStudio/E51FPGA/global_interrupts/global_interrupts Debug.launch)1
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/.cproject15
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/.project154
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch (renamed from FreedomStudio/E51FPGA/local_interrupts/local_interrupts Debug.launch)1
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/.cproject15
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/.project154
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch (renamed from FreedomStudio/E51FPGA/performance_counters/performance_counters Debug.launch)3
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/.cproject15
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/.project154
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json1230
-rw-r--r--FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch3
-rw-r--r--FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject193
-rw-r--r--FreedomStudio/E51FPGA/wrap-E51FPGA/.project253
29 files changed, 8797 insertions, 593 deletions
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 514d098..7da94d5 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.427474672" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
@@ -52,10 +52,6 @@
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
@@ -65,10 +61,6 @@
<listOptionValue builtIn="false" value="NO_INIT"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
@@ -83,16 +75,15 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c"/>
- <listOptionValue builtIn="false" value="wrap-E51FPGA"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
<listOptionValue builtIn="false" value="../"/>
</option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
</option>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.project b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
index 591c4d9..e2d1392 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.project
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
@@ -35,11 +35,6 @@
<locationURI>PARENT-3-PROJECT_LOC/software/coreplexip_welcome/coreplexip_welcome.c</locationURI>
</link>
<link>
- <name>bsp/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/drivers</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
@@ -55,9 +50,9 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/drivers/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>bsp/drivers/fe300prci</name>
@@ -70,11 +65,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/env/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/env/coreplexip-arty.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
@@ -105,12 +95,22 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
</link>
<link>
- <name>bsp/include/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/include/sifive</name>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
@@ -185,6 +185,126 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
</link>
<link>
+ <name>bsp/libwrap/misc/write_hex.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib/malloc.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/_exit.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/close.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/execve.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fork.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fstat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/getpid.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/isatty.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/kill.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/link.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/lseek.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/open.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/openat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/puts.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/read.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/sbrk.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stub.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/times.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/unlink.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/wait.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/weak_under_alias.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/write.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+ </link>
+ <link>
<name>bsp/include/sifive/devices/aon.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
index 81a28b7..9d170a8 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
@@ -1,5 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals&gt;&#10;&lt;peripheral name=&quot;gpio&quot;/&gt;&#10;&lt;/peripherals&gt;&#10;"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
@@ -20,6 +21,7 @@
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/dhrystone/.cproject b/FreedomStudio/E51FPGA/dhrystone/.cproject
new file mode 100644
index 0000000..f27d03f
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/.cproject
@@ -0,0 +1,213 @@
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+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1826132396" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+ </tool>
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+ <storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
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+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.1683678794" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.size" valueType="enumerated"/>
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+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.190439479" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" value="rm" valueType="string"/>
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+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1852055175" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.684576923" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
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+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.743554394" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
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+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler.351634096" name="GNU RISC-V Cross C++ Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.compiler"/>
+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.1633934157" name="GNU RISC-V Cross C Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker">
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections.1696261404" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.gcsections" value="true" valueType="boolean"/>
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+ </tool>
+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.2097010512" name="GNU RISC-V Cross C++ Linker" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker">
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.446955466" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
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+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1446800331" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.917780362" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
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+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.453203469" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" value="true" valueType="boolean"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.511548754" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" value="true" valueType="boolean"/>
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+ <tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.1315189209" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1728208687" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.743554394;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2132640858">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.424460842;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1695943366">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Debug">
+ <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
+ </configuration>
+ <configuration configurationName="Release">
+ <resource resourceType="PROJECT" workspacePath="/coreplexip_welcome"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+</cproject>
diff --git a/FreedomStudio/E51FPGA/wrap-E51FPGA/.gitignore b/FreedomStudio/E51FPGA/dhrystone/.gitignore
index 3df573f..3df573f 100644
--- a/FreedomStudio/E51FPGA/wrap-E51FPGA/.gitignore
+++ b/FreedomStudio/E51FPGA/dhrystone/.gitignore
diff --git a/FreedomStudio/E51FPGA/dhrystone/.project b/FreedomStudio/E51FPGA/dhrystone/.project
new file mode 100644
index 0000000..3683b2b
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/.project
@@ -0,0 +1,378 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>dhrystone</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>bsp</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>dhry.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry.h</locationURI>
+ </link>
+ <link>
+ <name>dhry_1.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_1.c</locationURI>
+ </link>
+ <link>
+ <name>dhry_2.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_2.c</locationURI>
+ </link>
+ <link>
+ <name>dhry_printf.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_printf.c</locationURI>
+ </link>
+ <link>
+ <name>dhry_stubs.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/software/dhrystone/dhry_stubs.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/drivers</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/env</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/include</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/drivers/fe300prci</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/drivers/plic</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/env/coreplexip-arty.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/env/coreplexip-e51-arty</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/env/encoding.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/env/entry.S</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI>
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+ <link>
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+ <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI>
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+ <name>bsp/env/start.S</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
+ </link>
+ <link>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
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+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/drivers/fe300prci/fe300prci_driver.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/drivers/plic/plic_driver.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c</locationURI>
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+ <locationURI>virtual:/virtual</locationURI>
+ </link>
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+ <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
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+ </link>
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+ </link>
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+ </link>
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+ </link>
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+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
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+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
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+ </link>
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+ </link>
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+ </link>
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+ </link>
+ <link>
+ <name>bsp/include/sifive/devices/uart.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml b/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml
new file mode 100644
index 0000000..d44fee0
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-127277270154718449" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.188392491" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-216478794982700293" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch
new file mode 100644
index 0000000..199c9c6
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/dhrystone OpenOCD.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
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diff --git a/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json b/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg
new file mode 100644
index 0000000..8b382dc
--- /dev/null
+++ b/FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg
@@ -0,0 +1,31 @@
+# JTAG adapter setup
+adapter_khz 10000
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+# Un-comment these two flash lines if you have a SPI flash and want to write
+# it.
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+ ftdi_set_signal nSRST 0
+ ftdi_set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
diff --git a/FreedomStudio/E51FPGA/global_interrupts/.cproject b/FreedomStudio/E51FPGA/global_interrupts/.cproject
index fc04722..672c12d 100644
--- a/FreedomStudio/E51FPGA/global_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/global_interrupts/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
@@ -52,10 +52,6 @@
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
@@ -65,10 +61,6 @@
<listOptionValue builtIn="false" value="USE_LOCAL_ISR"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
@@ -83,16 +75,15 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c"/>
- <listOptionValue builtIn="false" value="wrap-E51FPGA"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
<listOptionValue builtIn="false" value="../"/>
</option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
</option>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/global_interrupts/.project b/FreedomStudio/E51FPGA/global_interrupts/.project
index 516bd98..32aca6a 100644
--- a/FreedomStudio/E51FPGA/global_interrupts/.project
+++ b/FreedomStudio/E51FPGA/global_interrupts/.project
@@ -35,11 +35,6 @@
<locationURI>PARENT-3-PROJECT_LOC/software/global_interrupts/global_interrupts.c</locationURI>
</link>
<link>
- <name>bsp/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/drivers</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
@@ -55,9 +50,9 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/drivers/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>bsp/drivers/fe300prci</name>
@@ -70,11 +65,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/env/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/env/coreplexip-arty.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
@@ -105,12 +95,22 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
</link>
<link>
- <name>bsp/include/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/include/sifive</name>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
@@ -185,6 +185,126 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
</link>
<link>
+ <name>bsp/libwrap/misc/write_hex.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib/malloc.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/_exit.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/close.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/execve.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fork.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fstat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/getpid.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/isatty.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/kill.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/link.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/lseek.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/open.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/openat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/puts.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/read.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/sbrk.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stub.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/times.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/unlink.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/wait.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/weak_under_alias.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/write.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+ </link>
+ <link>
<name>bsp/include/sifive/devices/aon.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
diff --git a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts Debug.launch b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
index 93d9f58..6a7abd3 100644
--- a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts Debug.launch
+++ b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/.cproject b/FreedomStudio/E51FPGA/local_interrupts/.cproject
index fc04722..672c12d 100644
--- a/FreedomStudio/E51FPGA/local_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/local_interrupts/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
@@ -52,10 +52,6 @@
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
@@ -65,10 +61,6 @@
<listOptionValue builtIn="false" value="USE_LOCAL_ISR"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
@@ -83,16 +75,15 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c"/>
- <listOptionValue builtIn="false" value="wrap-E51FPGA"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
<listOptionValue builtIn="false" value="../"/>
</option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
</option>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/.project b/FreedomStudio/E51FPGA/local_interrupts/.project
index 0a46062..e70b49a 100644
--- a/FreedomStudio/E51FPGA/local_interrupts/.project
+++ b/FreedomStudio/E51FPGA/local_interrupts/.project
@@ -35,11 +35,6 @@
<locationURI>PARENT-3-PROJECT_LOC/software/local_interrupts/local_interrupts.c</locationURI>
</link>
<link>
- <name>bsp/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/drivers</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
@@ -55,9 +50,9 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/drivers/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>bsp/drivers/fe300prci</name>
@@ -70,11 +65,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/env/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/env/coreplexip-arty.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
@@ -105,12 +95,22 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
</link>
<link>
- <name>bsp/include/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/include/sifive</name>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
@@ -185,6 +185,126 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
</link>
<link>
+ <name>bsp/libwrap/misc/write_hex.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib/malloc.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/_exit.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/close.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/execve.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fork.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fstat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/getpid.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/isatty.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/kill.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/link.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/lseek.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/open.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/openat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/puts.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/read.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/sbrk.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stub.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/times.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/unlink.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/wait.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/weak_under_alias.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/write.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+ </link>
+ <link>
<name>bsp/include/sifive/devices/aon.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts Debug.launch b/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
index 04cb6e6..e03495c 100644
--- a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts Debug.launch
+++ b/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/performance_counters/.cproject b/FreedomStudio/E51FPGA/performance_counters/.cproject
index 84f7a26..6a5801a 100644
--- a/FreedomStudio/E51FPGA/performance_counters/.cproject
+++ b/FreedomStudio/E51FPGA/performance_counters/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
@@ -52,10 +52,6 @@
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
@@ -63,10 +59,6 @@
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.424460842" name="GNU RISC-V Cross C Compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler">
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs.1682056018" name="Defined symbols (-D)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.defs" useByScannerDiscovery="true"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
@@ -81,16 +73,15 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c"/>
- <listOptionValue builtIn="false" value="wrap-E51FPGA"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
<listOptionValue builtIn="false" value="../"/>
</option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
</option>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/performance_counters/.project b/FreedomStudio/E51FPGA/performance_counters/.project
index 080e602..ab25a9b 100644
--- a/FreedomStudio/E51FPGA/performance_counters/.project
+++ b/FreedomStudio/E51FPGA/performance_counters/.project
@@ -35,11 +35,6 @@
<locationURI>PARENT-3-PROJECT_LOC/software/performance_counters/performance_counters.c</locationURI>
</link>
<link>
- <name>bsp/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/drivers</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
@@ -55,9 +50,9 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/drivers/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>bsp/drivers/fe300prci</name>
@@ -70,11 +65,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/env/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/env/coreplexip-arty.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
@@ -105,12 +95,22 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
</link>
<link>
- <name>bsp/include/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/include/sifive</name>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
@@ -185,6 +185,126 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
</link>
<link>
+ <name>bsp/libwrap/misc/write_hex.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib/malloc.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/_exit.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/close.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/execve.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fork.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fstat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/getpid.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/isatty.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/kill.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/link.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/lseek.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/open.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/openat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/puts.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/read.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/sbrk.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stub.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/times.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/unlink.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/wait.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/weak_under_alias.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/write.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+ </link>
+ <link>
<name>bsp/include/sifive/devices/aon.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
diff --git a/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json b/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/performance_counters/performance_counters Debug.launch b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
index 4b980ad..75f80ba 100644
--- a/FreedomStudio/E51FPGA/performance_counters/performance_counters Debug.launch
+++ b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
@@ -20,6 +20,7 @@
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
@@ -54,6 +55,6 @@
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;&lt;memoryBlockExpression address=&quot;2147483648&quot; label=&quot;0x80000000&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
index c50fa56..747f474 100644
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
@@ -41,7 +41,7 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
@@ -52,10 +52,6 @@
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting.452480405" name="Generate assembler listing (-Wa,-adhlns=&quot;$@.lst&quot;)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -66,10 +62,6 @@
<listOptionValue builtIn="false" value="VECT_IRQ"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
- <listOptionValue builtIn="false" value="../bsp/drivers"/>
- <listOptionValue builtIn="false" value="../bsp/env"/>
- <listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
- <listOptionValue builtIn="false" value="../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/include"/>
<listOptionValue builtIn="false" value="../../../../bsp/env"/>
<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
@@ -84,16 +76,15 @@
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
<listOptionValue builtIn="false" value="c"/>
- <listOptionValue builtIn="false" value="wrap-E51FPGA"/>
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
- <listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
<listOptionValue builtIn="false" value="../"/>
</option>
- <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
</option>
+ <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.project b/FreedomStudio/E51FPGA/vectored_interrupts/.project
index 22e0667..f83b549 100644
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.project
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/.project
@@ -35,11 +35,6 @@
<locationURI>PARENT-3-PROJECT_LOC/software/vectored_interrupts/vectored_interrupts.c</locationURI>
</link>
<link>
- <name>bsp/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/drivers</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
@@ -55,9 +50,9 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/drivers/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
+ <name>bsp/libwrap</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>bsp/drivers/fe300prci</name>
@@ -70,11 +65,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/env/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
- </link>
- <link>
<name>bsp/env/coreplexip-arty.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h</locationURI>
@@ -105,12 +95,22 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/env/ventry.S</locationURI>
</link>
<link>
- <name>bsp/include/.DS_Store</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
+ <name>bsp/include/sifive</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
</link>
<link>
- <name>bsp/include/sifive</name>
+ <name>bsp/libwrap/misc</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
@@ -185,6 +185,126 @@
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
</link>
<link>
+ <name>bsp/libwrap/misc/write_hex.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/stdlib/malloc.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/_exit.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/close.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/execve.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fork.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/fstat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/getpid.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/isatty.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/kill.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/link.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/lseek.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/open.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/openat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/puts.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/read.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/sbrk.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stat.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/stub.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/times.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/unlink.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/wait.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/weak_under_alias.h</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+ </link>
+ <link>
+ <name>bsp/libwrap/sys/write.c</name>
+ <type>1</type>
+ <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+ </link>
+ <link>
<name>bsp/include/sifive/devices/aon.h</name>
<type>1</type>
<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e51arty": {
+ "displayName": "Core Complex E51 Arty",
+ "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "64",
+ "resetMask": "all",
+ "resetValue": "0x0000000000000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+ "headerTypePrefix": "sifive_e51arty_",
+ "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e51": {
+ "harts": "1",
+ "isa": "RV64IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ },
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "regWidth": "64"
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "regWidth": "64"
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "16",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "16",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
index b25a5d2..6d29781 100644
--- a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
@@ -7,7 +7,7 @@
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
@@ -20,6 +20,7 @@
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject b/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject
deleted file mode 100644
index 5eaec6b..0000000
--- a/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject
+++ /dev/null
@@ -1,193 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
- <storageModule moduleId="org.eclipse.cdt.core.settings">
- <cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.lib.debug.1605886310">
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- <externalSettings>
- <externalSetting>
- <entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/wrap-E51FPGA"/>
- <entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/wrap-E51FPGA/Debug"/>
- <entry flags="RESOLVED" kind="libraryFile" name="wrap-E51FPGA" srcPrefixMapping="" srcRootPath=""/>
- </externalSetting>
- </externalSettings>
- <extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
- <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
- <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
- </extensions>
- </storageModule>
- <storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.lib.debug.1605886310" name="Debug" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.lib.debug">
- <folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.lib.debug.1605886310." name="/" resourcePath="">
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- <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-</cproject>
diff --git a/FreedomStudio/E51FPGA/wrap-E51FPGA/.project b/FreedomStudio/E51FPGA/wrap-E51FPGA/.project
deleted file mode 100644
index db837eb..0000000
--- a/FreedomStudio/E51FPGA/wrap-E51FPGA/.project
+++ /dev/null
@@ -1,253 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
- <name>wrap-E51FPGA</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
- <triggers>full,incremental,</triggers>
- <arguments>
- </arguments>
- </buildCommand>
- </buildSpec>
- <natures>
- <nature>org.eclipse.cdt.core.cnature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
- <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
- </natures>
- <linkedResources>
- <link>
- <name>misc</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>stdlib</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>sys</name>
- <type>2</type>
- <locationURI>virtual:/virtual</locationURI>
- </link>
- <link>
- <name>misc/write_hex.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
- </link>
- <link>
- <name>misc/write_hex.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.o</locationURI>
- </link>
- <link>
- <name>stdlib/malloc.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
- </link>
- <link>
- <name>stdlib/malloc.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.o</locationURI>
- </link>
- <link>
- <name>sys/_exit.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
- </link>
- <link>
- <name>sys/_exit.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.o</locationURI>
- </link>
- <link>
- <name>sys/close.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
- </link>
- <link>
- <name>sys/close.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.o</locationURI>
- </link>
- <link>
- <name>sys/execve.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
- </link>
- <link>
- <name>sys/execve.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.o</locationURI>
- </link>
- <link>
- <name>sys/fork.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
- </link>
- <link>
- <name>sys/fork.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.o</locationURI>
- </link>
- <link>
- <name>sys/fstat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
- </link>
- <link>
- <name>sys/fstat.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.o</locationURI>
- </link>
- <link>
- <name>sys/getpid.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
- </link>
- <link>
- <name>sys/getpid.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.o</locationURI>
- </link>
- <link>
- <name>sys/isatty.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
- </link>
- <link>
- <name>sys/isatty.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.o</locationURI>
- </link>
- <link>
- <name>sys/kill.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
- </link>
- <link>
- <name>sys/kill.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.o</locationURI>
- </link>
- <link>
- <name>sys/link.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
- </link>
- <link>
- <name>sys/link.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.o</locationURI>
- </link>
- <link>
- <name>sys/lseek.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
- </link>
- <link>
- <name>sys/lseek.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.o</locationURI>
- </link>
- <link>
- <name>sys/open.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
- </link>
- <link>
- <name>sys/open.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.o</locationURI>
- </link>
- <link>
- <name>sys/openat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
- </link>
- <link>
- <name>sys/read.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
- </link>
- <link>
- <name>sys/read.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.o</locationURI>
- </link>
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- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
- </link>
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- <name>sys/sbrk.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.o</locationURI>
- </link>
- <link>
- <name>sys/stat.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
- </link>
- <link>
- <name>sys/stat.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.o</locationURI>
- </link>
- <link>
- <name>sys/stub.h</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
- </link>
- <link>
- <name>sys/times.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
- </link>
- <link>
- <name>sys/times.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.o</locationURI>
- </link>
- <link>
- <name>sys/unlink.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
- </link>
- <link>
- <name>sys/unlink.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.o</locationURI>
- </link>
- <link>
- <name>sys/wait.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
- </link>
- <link>
- <name>sys/wait.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.o</locationURI>
- </link>
- <link>
- <name>sys/write.c</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
- </link>
- <link>
- <name>sys/write.o</name>
- <type>1</type>
- <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.o</locationURI>
- </link>
- </linkedResources>
-</projectDescription>