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diff --git a/bsp/coreip-e20-arty/README.md b/bsp/coreip-e20-arty/README.md deleted file mode 100644 index a10a36c..0000000 --- a/bsp/coreip-e20-arty/README.md +++ /dev/null @@ -1,13 +0,0 @@ -The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. - -This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV32IMC core -- 4 hardware breakpoints -- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels -- GPIO memory with 16 interrupt lines -- SPI memory with 1 interrupt line -- Serial port with 1 interrupt line -- 4 RGB LEDS -- 4 Buttons and 4 Switches - |