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diff --git a/bsp/coreip-e20-rtl/README.md b/bsp/coreip-e20-rtl/README.md new file mode 100644 index 0000000..f908327 --- /dev/null +++ b/bsp/coreip-e20-rtl/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMC core +- 4 hardware breakpoints |