diff options
Diffstat (limited to 'bsp/coreip-e20-rtl')
| -rw-r--r-- | bsp/coreip-e20-rtl/metal-inline.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/metal-platform.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/metal.default.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/metal.h | 10 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/metal.ramrodata.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/metal.scratchpad.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/settings.mk | 4 |
7 files changed, 16 insertions, 11 deletions
diff --git a/bsp/coreip-e20-rtl/metal-inline.h b/bsp/coreip-e20-rtl/metal-inline.h index a896131..8f6f5d3 100644 --- a/bsp/coreip-e20-rtl/metal-inline.h +++ b/bsp/coreip-e20-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h index 4aa40ea..fd91dd9 100644 --- a/bsp/coreip-e20-rtl/metal-platform.h +++ b/bsp/coreip-e20-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef COREIP_E20_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds index 7937b08..3015cee 100644 --- a/bsp/coreip-e20-rtl/metal.default.lds +++ b/bsp/coreip-e20-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h index 6749faa..c7b2850 100644 --- a/bsp/coreip-e20-rtl/metal.h +++ b/bsp/coreip-e20-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -63,11 +63,11 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv_cpu.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,clic0.h> -#include <metal/drivers/sifive,local-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_clic0.h> +#include <metal/drivers/sifive_local-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_testram_20000000; diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds index 2343ee7..c9054d5 100644 --- a/bsp/coreip-e20-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds index 7937b08..3015cee 100644 --- a/bsp/coreip-e20-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-05-53 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index a935127..1d26ee1 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-05-53 # # ----------------------------------- # RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow +RISCV_SERIES=sifive-2-series COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 |