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Diffstat (limited to 'bsp/coreip-e20')
| -rw-r--r-- | bsp/coreip-e20/README.md | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md index 5e19221..4c9fe1a 100644 --- a/bsp/coreip-e20/README.md +++ b/bsp/coreip-e20/README.md @@ -1,6 +1,7 @@ The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 4 regions + +- 1 hart with RV32IMC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 4 regions |