diff options
Diffstat (limited to 'bsp/coreip-e21-arty/README.md')
| -rw-r--r-- | bsp/coreip-e21-arty/README.md | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/bsp/coreip-e21-arty/README.md b/bsp/coreip-e21-arty/README.md deleted file mode 100644 index e0cb9a7..0000000 --- a/bsp/coreip-e21-arty/README.md +++ /dev/null @@ -1,14 +0,0 @@ -The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. - -This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV32IMAC core -- 4 hardware breakpoints -- Physical Memory Protection with 4 regions -- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels -- GPIO memory with 16 interrupt lines -- SPI memory with 1 interrupt line -- Serial port with 1 interrupt line -- 4 RGB LEDS -- 4 Buttons and 4 Switches - |