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diff --git a/bsp/coreip-e21-arty/README.md b/bsp/coreip-e21-arty/README.md new file mode 100644 index 0000000..e0cb9a7 --- /dev/null +++ b/bsp/coreip-e21-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches + |