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-rw-r--r--bsp/coreip-e21-arty/design.dts5
-rw-r--r--bsp/coreip-e21-arty/metal-inline.h9
-rw-r--r--bsp/coreip-e21-arty/metal-platform.h7
-rw-r--r--bsp/coreip-e21-arty/metal.default.lds3
-rw-r--r--bsp/coreip-e21-arty/metal.h27
-rw-r--r--bsp/coreip-e21-arty/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-e21-arty/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-e21-arty/settings.mk2
8 files changed, 35 insertions, 24 deletions
diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts
index 7303568..40f61d0 100644
--- a/bsp/coreip-e21-arty/design.dts
+++ b/bsp/coreip-e21-arty/design.dts
@@ -21,6 +21,7 @@
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imac";
+ riscv,pmpregions = <4>;
status = "okay";
timebase-frequency = <32000000>;
hardware-exec-breakpoint-count = <4>;
@@ -36,10 +37,6 @@
#size-cells = <1>;
compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <4>;
- };
hfclk: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h
index 0f167d5..21116c7 100644
--- a/bsp/coreip-e21-arty/metal-inline.h
+++ b/bsp/coreip-e21-arty/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -23,8 +23,10 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *
/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu);
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
/* --------------------- sifive_plic0 ------------ */
@@ -173,11 +175,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
.init_done = 0,
};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
/* From interrupt_controller@2000000 */
struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
.controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h
index 75dc2dd..3e275a2 100644
--- a/bsp/coreip-e21-arty/metal-platform.h
+++ b/bsp/coreip-e21-arty/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef COREIP_E21_ARTY__METAL_PLATFORM_H
@@ -12,11 +12,6 @@
#define METAL_FIXED_CLOCK
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL
-
-#define METAL_RISCV_PMP
-
/* From interrupt_controller@2000000 */
#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
#define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds
index 0b7a37a..5bea1f5 100644
--- a/bsp/coreip-e21-arty/metal.default.lds
+++ b/bsp/coreip-e21-arty/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h
index 89b2931..f5e9533 100644
--- a/bsp/coreip-e21-arty/metal.h
+++ b/bsp/coreip-e21-arty/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0;
struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
/* From interrupt_controller@2000000 */
struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
@@ -174,6 +174,16 @@ static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock *
/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 0;
+ }
+ else {
+ return -1;
+ }
+}
+
static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
{
if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
@@ -194,6 +204,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
}
}
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 4;
+ }
+ else {
+ return 0;
+ }
+}
+
/* --------------------- sifive_plic0 ------------ */
@@ -1226,8 +1246,7 @@ asm (".weak __metal_cpu_table");
struct __metal_driver_cpu *__metal_cpu_table[] = {
&__metal_dt_cpu_0};
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
/* From interrupt_controller@2000000 */
#define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller)
diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds
index e1e793f..1e37ef6 100644
--- a/bsp/coreip-e21-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e21-arty/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds
index e986066..21e626f 100644
--- a/bsp/coreip-e21-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e21-arty/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk
index 3e8ebf8..ab96737 100644
--- a/bsp/coreip-e21-arty/settings.mk
+++ b/bsp/coreip-e21-arty/settings.mk
@@ -1,7 +1,7 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 22-05-2019 00-09-02 #
+# [XXXXX] 23-05-2019 13-29-49 #
# ----------------------------------- #
RISCV_ARCH=rv32imac
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 20:57:00 +0000