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diff --git a/bsp/coreip-e21-rtl/README.md b/bsp/coreip-e21-rtl/README.md new file mode 100644 index 0000000..6b74a44 --- /dev/null +++ b/bsp/coreip-e21-rtl/README.md @@ -0,0 +1,7 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions |