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Diffstat (limited to 'bsp/coreip-e21')
| -rw-r--r-- | bsp/coreip-e21/README.md | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md index 31719b3..a2f1a61 100644 --- a/bsp/coreip-e21/README.md +++ b/bsp/coreip-e21/README.md @@ -1,6 +1,7 @@ The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 4 regions + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 4 regions |