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-rw-r--r--bsp/coreip-e24-arty/design.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts
index 780cc7b..9699fae 100644
--- a/bsp/coreip-e24-arty/design.dts
+++ b/bsp/coreip-e24-arty/design.dts
@@ -23,6 +23,7 @@
riscv,isa = "rv32imafc";
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";