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diff --git a/bsp/coreip-e24/README.md b/bsp/coreip-e24/README.md new file mode 100644 index 0000000..1996262 --- /dev/null +++ b/bsp/coreip-e24/README.md @@ -0,0 +1,8 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions + |