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-rw-r--r--bsp/coreip-e31-arty/design.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts
index c69740e..03e100b 100644
--- a/bsp/coreip-e31-arty/design.dts
+++ b/bsp/coreip-e31-arty/design.dts
@@ -28,6 +28,7 @@
sifive,itim = <&L4>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";