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Diffstat (limited to 'bsp/coreip-e31-arty')
| -rw-r--r-- | bsp/coreip-e31-arty/README.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md index eeb3502..c6558cb 100644 --- a/bsp/coreip-e31-arty/README.md +++ b/bsp/coreip-e31-arty/README.md @@ -1,14 +1,14 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches |