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Diffstat (limited to 'bsp/coreip-e31')
| -rw-r--r-- | bsp/coreip-e31/README.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index 02f7723..ebfe371 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -1,9 +1,9 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -~ + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |