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diff --git a/bsp/coreip-e76/README.md b/bsp/coreip-e76/README.md new file mode 100644 index 0000000..cf5b465 --- /dev/null +++ b/bsp/coreip-e76/README.md @@ -0,0 +1,11 @@ +The SiFive E76 Standard Core is a high-performance 32-bit embedded processor which is fully-compliant with the RISC-V ISA. Its advanced memory subsystem enables inclusion of tightly-integrated memory and caches. + +The E76 is ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation). + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |