summaryrefslogtreecommitdiff
path: root/bsp/coreip-s51-arty
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/coreip-s51-arty')
-rw-r--r--bsp/coreip-s51-arty/README.md14
1 files changed, 14 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md
new file mode 100644
index 0000000..0290171
--- /dev/null
+++ b/bsp/coreip-s51-arty/README.md
@@ -0,0 +1,14 @@
+The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications
+
+This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports:
+
+- 1 hart with RV64IMAC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 interrupt line
+- Serial port with 1 interrupt line
+- 4 RGB LEDS
+- 4 Buttons and 4 Switches