summaryrefslogtreecommitdiff
path: root/bsp/coreip-s51-rtl
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/coreip-s51-rtl')
-rw-r--r--bsp/coreip-s51-rtl/metal-inline.h2
-rw-r--r--bsp/coreip-s51-rtl/metal-platform.h2
-rw-r--r--bsp/coreip-s51-rtl/metal.default.lds3
-rw-r--r--bsp/coreip-s51-rtl/metal.h14
-rw-r--r--bsp/coreip-s51-rtl/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-s51-rtl/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-s51-rtl/settings.mk4
7 files changed, 18 insertions, 13 deletions
diff --git a/bsp/coreip-s51-rtl/metal-inline.h b/bsp/coreip-s51-rtl/metal-inline.h
index 43b1d7b..de53041 100644
--- a/bsp/coreip-s51-rtl/metal-inline.h
+++ b/bsp/coreip-s51-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
#ifndef ASSEMBLY
diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h
index 9d7ee51..3b810aa 100644
--- a/bsp/coreip-s51-rtl/metal-platform.h
+++ b/bsp/coreip-s51-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
#ifndef COREIP_S51_RTL__METAL_PLATFORM_H
diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds
index e5be410..e2a4eae 100644
--- a/bsp/coreip-s51-rtl/metal.default.lds
+++ b/bsp/coreip-s51-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h
index 3a90f6c..05dc4ff 100644
--- a/bsp/coreip-s51-rtl/metal.h
+++ b/bsp/coreip-s51-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -71,13 +71,13 @@
#include <metal/drivers/fixed-clock.h>
#include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
#include <metal/pmp.h>
-#include <metal/drivers/sifive,local-external-interrupts0.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,test0.h>
+#include <metal/drivers/sifive_local-external-interrupts0.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_test0.h>
struct metal_memory __metal_dt_mem_testram_20000000;
diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds
index e9f838a..e39e123 100644
--- a/bsp/coreip-s51-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds
index e46abb7..c6cde71 100644
--- a/bsp/coreip-s51-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-05 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk
index 12a8c2e..b166dd3 100644
--- a/bsp/coreip-s51-rtl/settings.mk
+++ b/bsp/coreip-s51-rtl/settings.mk
@@ -1,14 +1,16 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49 #
+# [XXXXX] 28-05-2019 10-06-05 #
# ----------------------------------- #
RISCV_ARCH=rv64imac
RISCV_ABI=lp64
RISCV_CMODEL=medany
+RISCV_SERIES=sifive-5-series
COREIP_MEM_WIDTH=64
TARGET_TAGS=rtl
TARGET_DHRY_ITERS=2000
+TARGET_CORE_ITERS=5