summaryrefslogtreecommitdiff
path: root/bsp/coreip-s51
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/coreip-s51')
-rw-r--r--bsp/coreip-s51/README.md2
-rw-r--r--bsp/coreip-s51/design.dts49
-rw-r--r--bsp/coreip-s51/metal.h134
-rw-r--r--bsp/coreip-s51/settings.mk2
4 files changed, 29 insertions, 158 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md
index 60f75bf..bf808d1 100644
--- a/bsp/coreip-s51/README.md
+++ b/bsp/coreip-s51/README.md
@@ -6,4 +6,4 @@ This core target is suitable with Verilog RTL for verification and running appli
- 4 hardware breakpoints
- Physical Memory Protection with 8 regions
- 16 local interrupts signal that can be connected to off core complex devices
-- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
diff --git a/bsp/coreip-s51/design.dts b/bsp/coreip-s51/design.dts
index 9cf3a29..bbbab4d 100644
--- a/bsp/coreip-s51/design.dts
+++ b/bsp/coreip-s51/design.dts
@@ -3,26 +3,26 @@
/ {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "SiFive,FE510G-dev", "fe510-dev", "sifive-dev";
- model = "SiFive,FE510G";
+ compatible = "SiFive,FS510G-dev", "fs510-dev", "sifive-dev";
+ model = "SiFive,FS510G";
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
- L6: cpu@0 {
+ L7: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
- reg = <0>;
+ reg = <0x0>;
riscv,isa = "rv64imac";
- sifive,dtim = <&L5>;
- sifive,itim = <&L4>;
+ sifive,dtim = <&L6>;
+ sifive,itim = <&L5>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
- L3: interrupt-controller {
+ L4: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
@@ -32,7 +32,7 @@
L14: soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus";
+ compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus";
ranges;
pmp: pmp@0 {
compatible = "riscv,pmp";
@@ -41,63 +41,62 @@
L12: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "simple-bus";
+ compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus";
ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>;
};
L11: axi4-sys-port@40000000 {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "simple-bus";
+ compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus";
ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0xf0 0x0>;
};
- L1: clint@2000000 {
+ L2: clint@2000000 {
compatible = "riscv,clint0";
- interrupts-extended = <&L3 3 &L3 7>;
+ interrupts-extended = <&L4 3 &L4 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
- L2: debug-controller@0 {
+ L3: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L3 65535>;
+ interrupts-extended = <&L4 65535>;
reg = <0x0 0x0 0x0 0x1000>;
reg-names = "control";
};
- L5: dtim@80000000 {
+ L6: dtim@80000000 {
compatible = "sifive,dtim0";
reg = <0x0 0x80000000 0x0 0x10000>;
reg-names = "mem";
};
- L8: error-device@3000 {
+ L0: error-device@3000 {
compatible = "sifive,error0";
reg = <0x0 0x3000 0x0 0x1000>;
- reg-names = "mem";
};
L9: global-external-interrupts {
compatible = "sifive,global-external-interrupts0";
- interrupt-parent = <&L0>;
- interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>;
+ interrupt-parent = <&L1>;
+ interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
};
- L0: interrupt-controller@c000000 {
+ L1: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
- interrupts-extended = <&L3 11>;
+ interrupts-extended = <&L4 11>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
- riscv,ndev = <255>;
+ riscv,ndev = <127>;
};
- L4: itim@8000000 {
+ L5: itim@8000000 {
compatible = "sifive,itim0";
reg = <0x0 0x8000000 0x0 0x4000>;
reg-names = "mem";
};
L10: local-external-interrupts-0 {
compatible = "sifive,local-external-interrupts0";
- interrupt-parent = <&L3>;
+ interrupt-parent = <&L4>;
interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
};
- L7: teststatus@4000 {
+ L8: teststatus@4000 {
compatible = "sifive,test0";
reg = <0x0 0x4000 0x0 0x1000>;
reg-names = "control";
diff --git a/bsp/coreip-s51/metal.h b/bsp/coreip-s51/metal.h
index 6ee7908..62512f2 100644
--- a/bsp/coreip-s51/metal.h
+++ b/bsp/coreip-s51/metal.h
@@ -25,9 +25,9 @@
#define METAL_MAX_LOCAL_EXT_INTERRUPTS 16
-#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 255
+#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 127
-#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 255
+#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 127
#define METAL_MAX_GPIO_INTERRUPTS 0
@@ -115,7 +115,7 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
.control_base = 201326592UL,
.control_size = 67108864UL,
.max_priority = 7UL,
- .num_interrupts = 255UL,
+ .num_interrupts = 127UL,
.interrupt_controller = 1,
};
@@ -285,134 +285,6 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter
.interrupt_lines[124] = 125,
.interrupt_lines[125] = 126,
.interrupt_lines[126] = 127,
- .interrupt_lines[127] = 128,
- .interrupt_lines[128] = 129,
- .interrupt_lines[129] = 130,
- .interrupt_lines[130] = 131,
- .interrupt_lines[131] = 132,
- .interrupt_lines[132] = 133,
- .interrupt_lines[133] = 134,
- .interrupt_lines[134] = 135,
- .interrupt_lines[135] = 136,
- .interrupt_lines[136] = 137,
- .interrupt_lines[137] = 138,
- .interrupt_lines[138] = 139,
- .interrupt_lines[139] = 140,
- .interrupt_lines[140] = 141,
- .interrupt_lines[141] = 142,
- .interrupt_lines[142] = 143,
- .interrupt_lines[143] = 144,
- .interrupt_lines[144] = 145,
- .interrupt_lines[145] = 146,
- .interrupt_lines[146] = 147,
- .interrupt_lines[147] = 148,
- .interrupt_lines[148] = 149,
- .interrupt_lines[149] = 150,
- .interrupt_lines[150] = 151,
- .interrupt_lines[151] = 152,
- .interrupt_lines[152] = 153,
- .interrupt_lines[153] = 154,
- .interrupt_lines[154] = 155,
- .interrupt_lines[155] = 156,
- .interrupt_lines[156] = 157,
- .interrupt_lines[157] = 158,
- .interrupt_lines[158] = 159,
- .interrupt_lines[159] = 160,
- .interrupt_lines[160] = 161,
- .interrupt_lines[161] = 162,
- .interrupt_lines[162] = 163,
- .interrupt_lines[163] = 164,
- .interrupt_lines[164] = 165,
- .interrupt_lines[165] = 166,
- .interrupt_lines[166] = 167,
- .interrupt_lines[167] = 168,
- .interrupt_lines[168] = 169,
- .interrupt_lines[169] = 170,
- .interrupt_lines[170] = 171,
- .interrupt_lines[171] = 172,
- .interrupt_lines[172] = 173,
- .interrupt_lines[173] = 174,
- .interrupt_lines[174] = 175,
- .interrupt_lines[175] = 176,
- .interrupt_lines[176] = 177,
- .interrupt_lines[177] = 178,
- .interrupt_lines[178] = 179,
- .interrupt_lines[179] = 180,
- .interrupt_lines[180] = 181,
- .interrupt_lines[181] = 182,
- .interrupt_lines[182] = 183,
- .interrupt_lines[183] = 184,
- .interrupt_lines[184] = 185,
- .interrupt_lines[185] = 186,
- .interrupt_lines[186] = 187,
- .interrupt_lines[187] = 188,
- .interrupt_lines[188] = 189,
- .interrupt_lines[189] = 190,
- .interrupt_lines[190] = 191,
- .interrupt_lines[191] = 192,
- .interrupt_lines[192] = 193,
- .interrupt_lines[193] = 194,
- .interrupt_lines[194] = 195,
- .interrupt_lines[195] = 196,
- .interrupt_lines[196] = 197,
- .interrupt_lines[197] = 198,
- .interrupt_lines[198] = 199,
- .interrupt_lines[199] = 200,
- .interrupt_lines[200] = 201,
- .interrupt_lines[201] = 202,
- .interrupt_lines[202] = 203,
- .interrupt_lines[203] = 204,
- .interrupt_lines[204] = 205,
- .interrupt_lines[205] = 206,
- .interrupt_lines[206] = 207,
- .interrupt_lines[207] = 208,
- .interrupt_lines[208] = 209,
- .interrupt_lines[209] = 210,
- .interrupt_lines[210] = 211,
- .interrupt_lines[211] = 212,
- .interrupt_lines[212] = 213,
- .interrupt_lines[213] = 214,
- .interrupt_lines[214] = 215,
- .interrupt_lines[215] = 216,
- .interrupt_lines[216] = 217,
- .interrupt_lines[217] = 218,
- .interrupt_lines[218] = 219,
- .interrupt_lines[219] = 220,
- .interrupt_lines[220] = 221,
- .interrupt_lines[221] = 222,
- .interrupt_lines[222] = 223,
- .interrupt_lines[223] = 224,
- .interrupt_lines[224] = 225,
- .interrupt_lines[225] = 226,
- .interrupt_lines[226] = 227,
- .interrupt_lines[227] = 228,
- .interrupt_lines[228] = 229,
- .interrupt_lines[229] = 230,
- .interrupt_lines[230] = 231,
- .interrupt_lines[231] = 232,
- .interrupt_lines[232] = 233,
- .interrupt_lines[233] = 234,
- .interrupt_lines[234] = 235,
- .interrupt_lines[235] = 236,
- .interrupt_lines[236] = 237,
- .interrupt_lines[237] = 238,
- .interrupt_lines[238] = 239,
- .interrupt_lines[239] = 240,
- .interrupt_lines[240] = 241,
- .interrupt_lines[241] = 242,
- .interrupt_lines[242] = 243,
- .interrupt_lines[243] = 244,
- .interrupt_lines[244] = 245,
- .interrupt_lines[245] = 246,
- .interrupt_lines[246] = 247,
- .interrupt_lines[247] = 248,
- .interrupt_lines[248] = 249,
- .interrupt_lines[249] = 250,
- .interrupt_lines[250] = 251,
- .interrupt_lines[251] = 252,
- .interrupt_lines[252] = 253,
- .interrupt_lines[253] = 254,
- .interrupt_lines[254] = 255,
};
/* From teststatus@4000 */
diff --git a/bsp/coreip-s51/settings.mk b/bsp/coreip-s51/settings.mk
index 002e8cd..553417e 100644
--- a/bsp/coreip-s51/settings.mk
+++ b/bsp/coreip-s51/settings.mk
@@ -1,3 +1,3 @@
RISCV_ARCH=rv64imac
RISCV_ABI=lp64
-COREIP_MEM_WIDTH=32
+COREIP_MEM_WIDTH=64
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 03:06:19 +0000