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diff --git a/bsp/coreip-s54-arty/README.md b/bsp/coreip-s54-arty/README.md new file mode 100644 index 0000000..762c776 --- /dev/null +++ b/bsp/coreip-s54-arty/README.md @@ -0,0 +1,16 @@ +The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities. + +The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches |