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Diffstat (limited to 'bsp/coreip-s54/README.md')
| -rw-r--r-- | bsp/coreip-s54/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s54/README.md b/bsp/coreip-s54/README.md index 07b7159..e04dcf5 100644 --- a/bsp/coreip-s54/README.md +++ b/bsp/coreip-s54/README.md @@ -8,4 +8,4 @@ This core target is suitable with Verilog RTL for verification and running appli - 4 hardware breakpoints - Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices -- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |