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-rw-r--r--bsp/coreip-s76-arty/design.dts5
-rw-r--r--bsp/coreip-s76-arty/metal-inline.h8
-rw-r--r--bsp/coreip-s76-arty/metal-platform.h7
-rw-r--r--bsp/coreip-s76-arty/metal.default.lds2
-rw-r--r--bsp/coreip-s76-arty/metal.h17
-rw-r--r--bsp/coreip-s76-arty/metal.ramrodata.lds2
-rw-r--r--bsp/coreip-s76-arty/metal.scratchpad.lds2
-rw-r--r--bsp/coreip-s76-arty/settings.mk2
8 files changed, 21 insertions, 24 deletions
diff --git a/bsp/coreip-s76-arty/design.dts b/bsp/coreip-s76-arty/design.dts
index b5af1f3..00ed9ee 100644
--- a/bsp/coreip-s76-arty/design.dts
+++ b/bsp/coreip-s76-arty/design.dts
@@ -28,6 +28,7 @@
next-level-cache = <&L14 &L15>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <65000000>;
hardware-exec-breakpoint-count = <4>;
@@ -47,10 +48,6 @@
#size-cells = <1>;
compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <1>;
- };
L2: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h
index 6d4d486..a4e44af 100644
--- a/bsp/coreip-s76-arty/metal-inline.h
+++ b/bsp/coreip-s76-arty/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
/* --------------------- sifive_plic0 ------------ */
@@ -174,11 +175,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
.init_done = 0,
};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
/* From global_external_interrupts */
struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
.irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h
index eda81f7..1e72316 100644
--- a/bsp/coreip-s76-arty/metal-platform.h
+++ b/bsp/coreip-s76-arty/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
#ifndef COREIP_S76_ARTY__METAL_PLATFORM_H
@@ -40,11 +40,6 @@
#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
#define METAL_RISCV_PLIC0_CLAIM 2097156UL
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
-
-#define METAL_RISCV_PMP
-
/* From global_external_interrupts */
#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds
index 5f18721..b9fd8c7 100644
--- a/bsp/coreip-s76-arty/metal.default.lds
+++ b/bsp/coreip-s76-arty/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h
index 7c64fc7..d948150 100644
--- a/bsp/coreip-s76-arty/metal.h
+++ b/bsp/coreip-s76-arty/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
/* From interrupt_controller@c000000 */
struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
/* From global_external_interrupts */
struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
@@ -257,6 +257,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
}
}
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 8;
+ }
+ else {
+ return 0;
+ }
+}
+
/* --------------------- sifive_plic0 ------------ */
@@ -891,8 +901,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = {
#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
/* From global_external_interrupts */
#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc)
diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds
index 2399c34..5a48635 100644
--- a/bsp/coreip-s76-arty/metal.ramrodata.lds
+++ b/bsp/coreip-s76-arty/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds
index f218377..5abe56e 100644
--- a/bsp/coreip-s76-arty/metal.scratchpad.lds
+++ b/bsp/coreip-s76-arty/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10 */
+/* [XXXXX] 21-05-2019 10-54-34 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk
index 4ce0f71..4b9dfb0 100644
--- a/bsp/coreip-s76-arty/settings.mk
+++ b/bsp/coreip-s76-arty/settings.mk
@@ -1,7 +1,7 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10 #
+# [XXXXX] 21-05-2019 10-54-34 #
# ----------------------------------- #
RISCV_ARCH=rv64imafdc
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 04:54:04 +0000