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diff --git a/bsp/coreip-s76-rtl/README.md b/bsp/coreip-s76-rtl/README.md deleted file mode 100644 index 9623a83..0000000 --- a/bsp/coreip-s76-rtl/README.md +++ /dev/null @@ -1,11 +0,0 @@ -The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. - -The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV64IMAFDC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |