diff options
Diffstat (limited to 'bsp/coreip-u54-rtl')
| -rw-r--r-- | bsp/coreip-u54-rtl/metal-inline.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal-platform.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal.default.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal.h | 14 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal.ramrodata.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/metal.scratchpad.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-u54-rtl/settings.mk | 4 |
7 files changed, 18 insertions, 13 deletions
diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h index 3d08799..ef0bfb8 100644 --- a/bsp/coreip-u54-rtl/metal-inline.h +++ b/bsp/coreip-u54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h index fb3d3b4..90a8585 100644 --- a/bsp/coreip-u54-rtl/metal-platform.h +++ b/bsp/coreip-u54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-50 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef COREIP_U54_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds index 93fc5a8..76c79e3 100644 --- a/bsp/coreip-u54-rtl/metal.default.lds +++ b/bsp/coreip-u54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h index 7e793bc..59cf0f9 100644 --- a/bsp/coreip-u54-rtl/metal.h +++ b/bsp/coreip-u54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,13 +69,13 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,fu540-c000,l2.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_fu540-c000_l2.h> struct metal_memory __metal_dt_mem_itim_1800000; diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds index 57b767a..d65ac02 100644 --- a/bsp/coreip-u54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds index 93fc5a8..76c79e3 100644 --- a/bsp/coreip-u54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-15 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 0); .init : diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk index 4cf87cb..2f1a8b2 100644 --- a/bsp/coreip-u54-rtl/settings.mk +++ b/bsp/coreip-u54-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-50 # +# [XXXXX] 28-05-2019 10-06-15 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-5-series COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 |