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-rw-r--r--bsp/coreip-u54-rtl/metal-inline.h8
-rw-r--r--bsp/coreip-u54-rtl/metal-platform.h7
-rw-r--r--bsp/coreip-u54-rtl/metal.default.lds2
-rw-r--r--bsp/coreip-u54-rtl/metal.h17
-rw-r--r--bsp/coreip-u54-rtl/metal.ramrodata.lds2
-rw-r--r--bsp/coreip-u54-rtl/metal.scratchpad.lds2
-rw-r--r--bsp/coreip-u54-rtl/settings.mk2
7 files changed, 20 insertions, 20 deletions
diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h
index 03d29e6..186c3ab 100644
--- a/bsp/coreip-u54-rtl/metal-inline.h
+++ b/bsp/coreip-u54-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
/* --------------------- sifive_plic0 ------------ */
@@ -136,11 +137,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
.init_done = 0,
};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
/* From global_external_interrupts */
struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
.irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h
index 562f263..8bc29b7 100644
--- a/bsp/coreip-u54-rtl/metal-platform.h
+++ b/bsp/coreip-u54-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
#ifndef COREIP_U54_RTL__METAL_PLATFORM_H
@@ -35,11 +35,6 @@
#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
#define METAL_RISCV_PLIC0_CLAIM 2097156UL
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
-
-#define METAL_RISCV_PMP
-
/* From cache_controller@2010000 */
#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds
index 3a5705a..7dbd4f1 100644
--- a/bsp/coreip-u54-rtl/metal.default.lds
+++ b/bsp/coreip-u54-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h
index 0621896..ee3c264 100644
--- a/bsp/coreip-u54-rtl/metal.h
+++ b/bsp/coreip-u54-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -92,7 +92,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
/* From interrupt_controller@c000000 */
struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
/* From global_external_interrupts */
struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
@@ -191,6 +191,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
}
}
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 8;
+ }
+ else {
+ return 0;
+ }
+}
+
/* --------------------- sifive_plic0 ------------ */
@@ -759,8 +769,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = {
#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
/* From global_external_interrupts */
#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc)
diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds
index 2873493..1fd5001 100644
--- a/bsp/coreip-u54-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds
index 3a5705a..7dbd4f1 100644
--- a/bsp/coreip-u54-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk
index 6c25a1f..3815c91 100644
--- a/bsp/coreip-u54-rtl/settings.mk
+++ b/bsp/coreip-u54-rtl/settings.mk
@@ -1,7 +1,7 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11 #
+# [XXXXX] 21-05-2019 10-54-35 #
# ----------------------------------- #
RISCV_ARCH=rv64imafdc