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-rw-r--r--bsp/coreip-u54mc-rtl/README.md23
-rw-r--r--bsp/coreip-u54mc-rtl/design.dts291
-rw-r--r--bsp/coreip-u54mc-rtl/metal-inline.h257
-rw-r--r--bsp/coreip-u54mc-rtl/metal-platform.h60
-rw-r--r--bsp/coreip-u54mc-rtl/metal.default.lds237
-rw-r--r--bsp/coreip-u54mc-rtl/metal.h1004
-rw-r--r--bsp/coreip-u54mc-rtl/metal.ramrodata.lds234
-rw-r--r--bsp/coreip-u54mc-rtl/metal.scratchpad.lds237
-rw-r--r--bsp/coreip-u54mc-rtl/settings.mk15
9 files changed, 0 insertions, 2358 deletions
diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md
deleted file mode 100644
index 1d26288..0000000
--- a/bsp/coreip-u54mc-rtl/README.md
+++ /dev/null
@@ -1,23 +0,0 @@
-The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
-
-The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking.
-
-This target features:
-
-- 4x RV64GC U54 Application Cores
- - 32KB L1 I-cache with ECC
- - 32KB L1 D-cache with ECC
- - 8 Region Physical Memory Protection
- - 48 Local Interrupts per core
- - Sv39 Virtual Memory support with 38 Physical Address bits
-- 1x RV64IMAC S51 Monitor Core
- - 16KB L1 I-Cache with ECC
- - 8KB DTIM with ECC
- - 8 Region Physical Memory Protection
- - 48 Local Interrupts
-- Fully Coherent TileLink Bus
-- Integrated 2MB L2 Cache with ECC
-- Real-time capabilities
-- CLINT for multi-core timer and software interrupts
-- PLIC with support for up to 511 interrupts with 7 priority levels
-- Debug with instruction trace
diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts
deleted file mode 100644
index beba177..0000000
--- a/bsp/coreip-u54mc-rtl/design.dts
+++ /dev/null
@@ -1,291 +0,0 @@
-/dts-v1/;
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev";
- model = "SiFive,FU540G";
- L36: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- L9: cpu@0 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- next-level-cache = <&L33>;
- reg = <0x0>;
- riscv,isa = "rv64imac";
- riscv,pmpregions = <8>;
- sifive,dtim = <&L7>;
- sifive,itim = <&L6>;
- status = "okay";
- timebase-frequency = <1000000>;
- L5: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- L13: cpu@1 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&L33>;
- reg = <0x1>;
- riscv,isa = "rv64imafdc";
- riscv,pmpregions = <8>;
- sifive,itim = <&L11>;
- status = "okay";
- timebase-frequency = <1000000>;
- tlb-split;
- L10: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- L17: cpu@2 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&L33>;
- reg = <0x2>;
- riscv,isa = "rv64imafdc";
- riscv,pmpregions = <8>;
- sifive,itim = <&L15>;
- status = "okay";
- timebase-frequency = <1000000>;
- tlb-split;
- L14: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- L21: cpu@3 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&L33>;
- reg = <0x3>;
- riscv,isa = "rv64imafdc";
- riscv,pmpregions = <8>;
- sifive,itim = <&L19>;
- status = "okay";
- timebase-frequency = <1000000>;
- tlb-split;
- L18: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- L25: cpu@4 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&L33>;
- reg = <0x4>;
- riscv,isa = "rv64imafdc";
- riscv,pmpregions = <8>;
- sifive,itim = <&L23>;
- status = "okay";
- timebase-frequency = <1000000>;
- tlb-split;
- L22: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- L28: memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x20000000>;
- };
- L35: soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
- ranges;
- L30: axi4-periph-port@20000000 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus";
- ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>;
- };
- L29: axi4-sys-port@40000000 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus";
- ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0x30 0x0>;
- };
- L8: bus-error-unit@1700000 {
- compatible = "sifive,buserror0";
- interrupt-parent = <&L2>;
- interrupts = <132>;
- reg = <0x0 0x1700000 0x0 0x1000>;
- reg-names = "control";
- };
- L12: bus-error-unit@1701000 {
- compatible = "sifive,buserror0";
- interrupt-parent = <&L2>;
- interrupts = <133>;
- reg = <0x0 0x1701000 0x0 0x1000>;
- reg-names = "control";
- };
- L16: bus-error-unit@1702000 {
- compatible = "sifive,buserror0";
- interrupt-parent = <&L2>;
- interrupts = <134>;
- reg = <0x0 0x1702000 0x0 0x1000>;
- reg-names = "control";
- };
- L20: bus-error-unit@1703000 {
- compatible = "sifive,buserror0";
- interrupt-parent = <&L2>;
- interrupts = <135>;
- reg = <0x0 0x1703000 0x0 0x1000>;
- reg-names = "control";
- };
- L24: bus-error-unit@1704000 {
- compatible = "sifive,buserror0";
- interrupt-parent = <&L2>;
- interrupts = <136>;
- reg = <0x0 0x1704000 0x0 0x1000>;
- reg-names = "control";
- };
- L33: cache-controller@2010000 {
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <2048>;
- cache-size = <2097152>;
- cache-unified;
- compatible = "sifive,ccache0", "cache";
- interrupt-parent = <&L2>;
- interrupts = <128 129 130 131>;
- next-level-cache = <&L0 &L28>;
- reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x200000>;
- reg-names = "control", "sideband";
- sifive,ecc-granularity = <8>;
- sifive,mshr-count = <6>;
- };
- L3: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&L5 3 &L5 7 &L10 3 &L10 7 &L14 3 &L14 7 &L18 3 &L18 7 &L22 3 &L22 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
- };
- L4: debug-controller@0 {
- compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L5 65535 &L10 65535 &L14 65535 &L18 65535 &L22 65535>;
- reg = <0x0 0x0 0x0 0x1000>;
- reg-names = "control";
- };
- L7: dtim@1000000 {
- compatible = "sifive,dtim0";
- reg = <0x0 0x1000000 0x0 0x2000>;
- reg-names = "mem";
- };
- L1: error-device@3000 {
- compatible = "sifive,error0";
- reg = <0x0 0x3000 0x0 0x1000>;
- };
- L27: global-external-interrupts {
- compatible = "sifive,global-external-interrupts0";
- interrupt-parent = <&L2>;
- interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
- };
- L2: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&L5 11 &L10 11 &L10 9 &L14 11 &L14 9 &L18 11 &L18 9 &L22 11 &L22 9>;
- reg = <0x0 0xc000000 0x0 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <136>;
- };
- L6: itim@1800000 {
- compatible = "sifive,itim0";
- reg = <0x0 0x1800000 0x0 0x4000>;
- reg-names = "mem";
- };
- L11: itim@1808000 {
- compatible = "sifive,itim0";
- reg = <0x0 0x1808000 0x0 0x8000>;
- reg-names = "mem";
- };
- L15: itim@1810000 {
- compatible = "sifive,itim0";
- reg = <0x0 0x1810000 0x0 0x8000>;
- reg-names = "mem";
- };
- L19: itim@1818000 {
- compatible = "sifive,itim0";
- reg = <0x0 0x1818000 0x0 0x8000>;
- reg-names = "mem";
- };
- L23: itim@1820000 {
- compatible = "sifive,itim0";
- reg = <0x0 0x1820000 0x0 0x8000>;
- reg-names = "mem";
- };
- L0: rom@a000000 {
- compatible = "ucbbar,cacheable-zero0";
- reg = <0x0 0xa000000 0x0 0x2000000>;
- };
- L26: teststatus@4000 {
- compatible = "sifive,test0";
- reg = <0x0 0x4000 0x0 0x1000>;
- reg-names = "control";
- };
- };
-};
diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h
deleted file mode 100644
index 3a5004d..0000000
--- a/bsp/coreip-u54mc-rtl/metal-inline.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-#ifndef ASSEMBLY
-
-#ifndef COREIP_U54MC_RTL__METAL_INLINE_H
-#define COREIP_U54MC_RTL__METAL_INLINE_H
-
-#include <metal/machine.h>
-
-
-/* --------------------- fixed_clock ------------ */
-
-
-/* --------------------- fixed_factor_clock ------------ */
-
-
-/* --------------------- sifive_clint0 ------------ */
-extern inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller);
-extern inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller);
-extern inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller);
-extern inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx);
-extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx);
-
-
-/* --------------------- cpu ------------ */
-extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu);
-extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
-extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
-extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
-
-
-/* --------------------- sifive_plic0 ------------ */
-extern inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller);
-extern inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller);
-extern inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller);
-extern inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller);
-extern inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx);
-extern inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx);
-
-
-/* --------------------- sifive_clic0 ------------ */
-
-
-/* --------------------- sifive_local_external_interrupts0 ------------ */
-
-
-/* --------------------- sifive_global_external_interrupts0 ------------ */
-extern inline int __metal_driver_sifive_global_external_interrupts0_init_done( );
-extern inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller);
-extern inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller);
-extern inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx);
-
-
-/* --------------------- sifive_gpio0 ------------ */
-
-
-/* --------------------- sifive_gpio_button ------------ */
-
-
-/* --------------------- sifive_gpio_led ------------ */
-
-
-/* --------------------- sifive_gpio_switch ------------ */
-
-
-/* --------------------- sifive_spi0 ------------ */
-
-
-/* --------------------- sifive_test0 ------------ */
-extern inline unsigned long __metal_driver_sifive_test0_base( );
-extern inline unsigned long __metal_driver_sifive_test0_size( );
-
-
-/* --------------------- sifive_uart0 ------------ */
-
-
-/* --------------------- sifive_fe310_g000_hfrosc ------------ */
-
-
-/* --------------------- sifive_fe310_g000_hfxosc ------------ */
-
-
-/* --------------------- sifive_fe310_g000_pll ------------ */
-
-
-/* --------------------- fe310_g000_prci ------------ */
-
-
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
-struct metal_memory __metal_dt_mem_dtim_1000000 = {
- ._base_address = 16777216UL,
- ._size = 8192UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1800000 = {
- ._base_address = 25165824UL,
- ._size = 16384UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1808000 = {
- ._base_address = 25198592UL,
- ._size = 32768UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1810000 = {
- ._base_address = 25231360UL,
- ._size = 32768UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1818000 = {
- ._base_address = 25264128UL,
- ._size = 32768UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_itim_1820000 = {
- ._base_address = 25296896UL,
- ._size = 32768UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-struct metal_memory __metal_dt_mem_memory_80000000 = {
- ._base_address = 2147483648UL,
- ._size = 536870912UL,
- ._attrs = {
- .R = 1,
- .W = 1,
- .X = 1,
- .C = 1,
- .A = 1},
-};
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = {
- .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable,
- .init_done = 0,
-};
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0 = {
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-};
-
-/* From cpu@1 */
-struct __metal_driver_cpu __metal_dt_cpu_1 = {
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-};
-
-/* From cpu@2 */
-struct __metal_driver_cpu __metal_dt_cpu_2 = {
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-};
-
-/* From cpu@3 */
-struct __metal_driver_cpu __metal_dt_cpu_3 = {
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-};
-
-/* From cpu@4 */
-struct __metal_driver_cpu __metal_dt_cpu_4 = {
- .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = {
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = {
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = {
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
-};
-
-/* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = {
- .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
- .init_done = 0,
-};
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
- .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable,
- .init_done = 0,
-};
-
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
- .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
- .init_done = 0,
-};
-
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
- .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
-};
-
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = {
- .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache,
-};
-
-
-#endif /* COREIP_U54MC_RTL__METAL_INLINE_H*/
-#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h
deleted file mode 100644
index 2c46b21..0000000
--- a/bsp/coreip-u54mc-rtl/metal-platform.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-#ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H
-#define COREIP_U54MC_RTL__METAL_PLATFORM_H
-
-/* From clint@2000000 */
-#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
-#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
-#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
-#define METAL_RISCV_CLINT0_0_SIZE 65536UL
-
-#define METAL_RISCV_CLINT0
-#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
-#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
-#define METAL_RISCV_CLINT0_MTIME 49144UL
-
-/* From interrupt_controller@c000000 */
-#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
-#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
-#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
-#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
-#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
-#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
-#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 137UL
-#define METAL_RISCV_PLIC0_0_RISCV_NDEV 137UL
-
-#define METAL_RISCV_PLIC0
-#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
-#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
-#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
-#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
-#define METAL_RISCV_PLIC0_CLAIM 2097156UL
-
-/* From cache_controller@2010000 */
-#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
-#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
-#define METAL_SIFIVE_FU540_C000_L2_2010000_SIZE 4096UL
-#define METAL_SIFIVE_FU540_C000_L2_0_SIZE 4096UL
-
-#define METAL_SIFIVE_FU540_C000_L2
-#define METAL_SIFIVE_FU540_C000_L2_CONFIG 0UL
-#define METAL_SIFIVE_FU540_C000_L2_WAYENABLE 8UL
-
-/* From global_external_interrupts */
-
-#define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
-
-/* From teststatus@4000 */
-#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
-#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 16384UL
-#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
-#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
-
-#define METAL_SIFIVE_TEST0
-#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
-
-#endif /* COREIP_U54MC_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds
deleted file mode 100644
index 3b03685..0000000
--- a/bsp/coreip-u54mc-rtl/metal.default.lds
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-OUTPUT_ARCH("riscv")
-
-ENTRY(_enter)
-
-MEMORY
-{
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
- itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- itim_init PT_LOAD;
- ram PT_LOAD;
- itim PT_LOAD;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
- PROVIDE(__stack_size = __stack_size);
- __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
- PROVIDE(__metal_boot_hart = 0);
- PROVIDE(__metal_chicken_bit = 0);
-
-
- .init :
- {
- KEEP (*(.text.metal.init.enter))
- KEEP (*(SORT_NONE(.init)))
- KEEP (*(.text.libgloss.start))
- } >ram AT>ram :ram
-
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >ram AT>ram :ram
-
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >ram AT>ram :ram
-
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>ram :ram
-
-
- . = ALIGN(4);
-
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >ram AT>ram :ram
-
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >ram AT>ram :ram
-
-
- .finit_array :
- {
- PROVIDE_HIDDEN (__finit_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__finit_array_end = .);
- } >ram AT>ram :ram
-
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >ram AT>ram :ram
-
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >ram AT>ram :ram
-
-
- .litimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_source_start = . );
- } >ram AT>ram :ram
-
-
- .ditimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_target_start = . );
- } >itim AT>ram :itim_init
-
-
- .itim :
- {
- *(.itim .itim.*)
- } >itim AT>ram :itim_init
-
-
- . = ALIGN(8);
- PROVIDE( metal_segment_itim_target_end = . );
-
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- PROVIDE( metal_segment_data_source_start = . );
- } >ram AT>ram :ram
-
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_data_target_start = . );
- } >ram AT>ram :ram_init
-
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.* .sdata2.*)
- *(.gnu.linkonce.s.*)
- } >ram AT>ram :ram_init
-
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
- PROVIDE( metal_segment_data_target_end = . );
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- PROVIDE( metal_segment_bss_target_start = . );
-
-
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
- PROVIDE( metal_segment_bss_target_end = . );
-
-
- .stack :
- {
- PROVIDE(metal_segment_stack_begin = .);
- . = __stack_size;
- PROVIDE( _sp = . );
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- PROVIDE(metal_segment_stack_end = .);
- } >ram AT>ram :ram
-
-
- .heap :
- {
- PROVIDE( metal_segment_heap_target_start = . );
- . = __heap_size;
- PROVIDE( metal_segment_heap_target_end = . );
- PROVIDE( _heap_end = . );
- } >ram AT>ram :ram
-
-
-}
-
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
deleted file mode 100644
index 23b900c..0000000
--- a/bsp/coreip-u54mc-rtl/metal.h
+++ /dev/null
@@ -1,1004 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-#ifndef ASSEMBLY
-
-#include <metal/machine/platform.h>
-
-#ifdef __METAL_MACHINE_MACROS
-
-#ifndef MACROS_IF_COREIP_U54MC_RTL__METAL_H
-#define MACROS_IF_COREIP_U54MC_RTL__METAL_H
-
-#define __METAL_CLINT_NUM_PARENTS 10
-
-#ifndef __METAL_CLINT_NUM_PARENTS
-#define __METAL_CLINT_NUM_PARENTS 0
-#endif
-#define __METAL_PLIC_SUBINTERRUPTS 137
-
-#define __METAL_PLIC_NUM_PARENTS 9
-
-#ifndef __METAL_PLIC_SUBINTERRUPTS
-#define __METAL_PLIC_SUBINTERRUPTS 0
-#endif
-#ifndef __METAL_PLIC_NUM_PARENTS
-#define __METAL_PLIC_NUM_PARENTS 0
-#endif
-#ifndef __METAL_CLIC_SUBINTERRUPTS
-#define __METAL_CLIC_SUBINTERRUPTS 0
-#endif
-
-#endif /* MACROS_IF_COREIP_U54MC_RTL__METAL_H*/
-
-#else /* ! __METAL_MACHINE_MACROS */
-
-#ifndef MACROS_ELSE_COREIP_U54MC_RTL__METAL_H
-#define MACROS_ELSE_COREIP_U54MC_RTL__METAL_H
-
-#define __METAL_CLINT_2000000_INTERRUPTS 10
-
-#define METAL_MAX_CLINT_INTERRUPTS 10
-
-#define __METAL_CLINT_NUM_PARENTS 10
-
-#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 9
-
-#define __METAL_PLIC_SUBINTERRUPTS 137
-
-#define METAL_MAX_PLIC_INTERRUPTS 9
-
-#define __METAL_PLIC_NUM_PARENTS 9
-
-#define __METAL_CLIC_SUBINTERRUPTS 0
-#define METAL_MAX_CLIC_INTERRUPTS 0
-
-#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0
-
-#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 127
-
-#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 127
-
-#define METAL_MAX_GPIO_INTERRUPTS 0
-
-#define METAL_MAX_UART_INTERRUPTS 0
-
-
-#include <metal/drivers/fixed-clock.h>
-#include <metal/memory.h>
-#include <metal/drivers/riscv_clint0.h>
-#include <metal/drivers/riscv_cpu.h>
-#include <metal/drivers/riscv_plic0.h>
-#include <metal/pmp.h>
-#include <metal/drivers/sifive_global-external-interrupts0.h>
-#include <metal/drivers/sifive_test0.h>
-#include <metal/drivers/sifive_fu540-c000_l2.h>
-
-struct metal_memory __metal_dt_mem_dtim_1000000;
-
-struct metal_memory __metal_dt_mem_itim_1800000;
-
-struct metal_memory __metal_dt_mem_itim_1808000;
-
-struct metal_memory __metal_dt_mem_itim_1810000;
-
-struct metal_memory __metal_dt_mem_itim_1818000;
-
-struct metal_memory __metal_dt_mem_itim_1820000;
-
-struct metal_memory __metal_dt_mem_memory_80000000;
-
-/* From clint@2000000 */
-struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000;
-
-/* From cpu@0 */
-struct __metal_driver_cpu __metal_dt_cpu_0;
-
-/* From cpu@1 */
-struct __metal_driver_cpu __metal_dt_cpu_1;
-
-/* From cpu@2 */
-struct __metal_driver_cpu __metal_dt_cpu_2;
-
-/* From cpu@3 */
-struct __metal_driver_cpu __metal_dt_cpu_3;
-
-/* From cpu@4 */
-struct __metal_driver_cpu __metal_dt_cpu_4;
-
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
-
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller;
-
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller;
-
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller;
-
-struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
-
-/* From interrupt_controller@c000000 */
-struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
-
-struct metal_pmp __metal_dt_pmp;
-
-/* From global_external_interrupts */
-struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
-
-/* From teststatus@4000 */
-struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
-
-/* From cache_controller@2010000 */
-struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000;
-
-
-
-/* --------------------- fixed_clock ------------ */
-
-
-/* --------------------- fixed_factor_clock ------------ */
-
-
-/* --------------------- sifive_clint0 ------------ */
-static inline unsigned long __metal_driver_sifive_clint0_control_base(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
- return METAL_RISCV_CLINT0_2000000_BASE_ADDRESS;
- }
- else {
- return 0;
- }
-}
-
-static inline unsigned long __metal_driver_sifive_clint0_control_size(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
- return METAL_RISCV_CLINT0_2000000_SIZE;
- }
- else {
- return 0;
- }
-}
-
-static inline int __metal_driver_sifive_clint0_num_interrupts(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_clint_2000000) {
- return METAL_MAX_CLINT_INTERRUPTS;
- }
- else {
- return 0;
- }
-}
-
-static inline struct metal_interrupt * __metal_driver_sifive_clint0_interrupt_parents(struct metal_interrupt *controller, int idx)
-{
- if (idx == 0) {
- return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if (idx == 1) {
- return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if (idx == 2) {
- return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
- }
- else if (idx == 3) {
- return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
- }
- else if (idx == 4) {
- return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
- }
- else if (idx == 5) {
- return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
- }
- else if (idx == 6) {
- return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
- }
- else if (idx == 7) {
- return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
- }
- else if (idx == 8) {
- return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
- }
- else if (idx == 9) {
- return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
- }
- else {
- return NULL;
- }
-}
-
-static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_interrupt *controller, int idx)
-{
- if (idx == 0) {
- return 3;
- }
- else if (idx == 1) {
- return 7;
- }
- else if (idx == 2) {
- return 3;
- }
- else if (idx == 3) {
- return 7;
- }
- else if (idx == 4) {
- return 3;
- }
- else if (idx == 5) {
- return 7;
- }
- else if (idx == 6) {
- return 3;
- }
- else if (idx == 7) {
- return 7;
- }
- else if (idx == 8) {
- return 3;
- }
- else if (idx == 9) {
- return 7;
- }
- else {
- return 0;
- }
-}
-
-
-
-/* --------------------- cpu ------------ */
-static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu)
-{
- if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 0;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 0;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
- return 1;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
- return 2;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
- return 3;
- }
- else {
- return -1;
- }
-}
-
-static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
-{
- if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 1000000;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 1000000;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
- return 1000000;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
- return 1000000;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
- return 1000000;
- }
- else {
- return 0;
- }
-}
-
-static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu)
-{
- if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return &__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return &__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
- return &__metal_dt_cpu_1_interrupt_controller.controller;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
- return &__metal_dt_cpu_2_interrupt_controller.controller;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
- return &__metal_dt_cpu_3_interrupt_controller.controller;
- }
- else {
- return NULL;
- }
-}
-
-static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
-{
- if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 8;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
- return 8;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
- return 8;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
- return 8;
- }
- else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
- return 8;
- }
- else {
- return 0;
- }
-}
-
-
-
-/* --------------------- sifive_plic0 ------------ */
-static inline unsigned long __metal_driver_sifive_plic0_control_base(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
- return METAL_RISCV_PLIC0_C000000_BASE_ADDRESS;
- }
- else {
- return 0;
- }
-}
-
-static inline unsigned long __metal_driver_sifive_plic0_control_size(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
- return METAL_RISCV_PLIC0_C000000_SIZE;
- }
- else {
- return 0;
- }
-}
-
-static inline int __metal_driver_sifive_plic0_num_interrupts(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
- return METAL_RISCV_PLIC0_C000000_RISCV_NDEV;
- }
- else {
- return 0;
- }
-}
-
-static inline int __metal_driver_sifive_plic0_max_priority(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_interrupt_controller_c000000) {
- return METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY;
- }
- else {
- return 0;
- }
-}
-
-static inline struct metal_interrupt * __metal_driver_sifive_plic0_interrupt_parents(struct metal_interrupt *controller, int idx)
-{
- if (idx == 0) {
- return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if (idx == 0) {
- return (struct metal_interrupt *)&__metal_dt_cpu_0_interrupt_controller.controller;
- }
- else if (idx == 1) {
- return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
- }
- else if (idx == 2) {
- return (struct metal_interrupt *)&__metal_dt_cpu_1_interrupt_controller.controller;
- }
- else if (idx == 3) {
- return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
- }
- else if (idx == 4) {
- return (struct metal_interrupt *)&__metal_dt_cpu_2_interrupt_controller.controller;
- }
- else if (idx == 5) {
- return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
- }
- else if (idx == 6) {
- return (struct metal_interrupt *)&__metal_dt_cpu_3_interrupt_controller.controller;
- }
- else if (idx == 7) {
- return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
- }
- else if (idx == 8) {
- return (struct metal_interrupt *)&__metal_dt_cpu_4_interrupt_controller.controller;
- }
- else {
- return NULL;
- }
-}
-
-static inline int __metal_driver_sifive_plic0_interrupt_lines(struct metal_interrupt *controller, int idx)
-{
- if (idx == 0) {
- return 11;
- }
- else if (idx == 0) {
- return 11;
- }
- else if (idx == 1) {
- return 11;
- }
- else if (idx == 2) {
- return 9;
- }
- else if (idx == 3) {
- return 11;
- }
- else if (idx == 4) {
- return 9;
- }
- else if (idx == 5) {
- return 11;
- }
- else if (idx == 6) {
- return 9;
- }
- else if (idx == 7) {
- return 11;
- }
- else if (idx == 8) {
- return 9;
- }
- else {
- return 0;
- }
-}
-
-
-
-/* --------------------- sifive_clic0 ------------ */
-
-
-/* --------------------- sifive_local_external_interrupts0 ------------ */
-
-
-/* --------------------- sifive_global_external_interrupts0 ------------ */
-static inline int __metal_driver_sifive_global_external_interrupts0_init_done()
-{
- return 0;
-}
-
-static inline struct metal_interrupt * __metal_driver_sifive_global_external_interrupts0_interrupt_parent(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
- return (struct metal_interrupt *)&__metal_dt_interrupt_controller_c000000.controller;
- }
- else {
- return NULL;
- }
-}
-
-static inline int __metal_driver_sifive_global_external_interrupts0_num_interrupts(struct metal_interrupt *controller)
-{
- if ((uintptr_t)controller == (uintptr_t)&__metal_dt_global_external_interrupts) {
- return METAL_MAX_GLOBAL_EXT_INTERRUPTS;
- }
- else {
- return 0;
- }
-}
-
-static inline int __metal_driver_sifive_global_external_interrupts0_interrupt_lines(struct metal_interrupt *controller, int idx)
-{
- if (idx == 0) {
- return 1;
- }
- else if (idx == 1) {
- return 2;
- }
- else if (idx == 2) {
- return 3;
- }
- else if (idx == 3) {
- return 4;
- }
- else if (idx == 4) {
- return 5;
- }
- else if (idx == 5) {
- return 6;
- }
- else if (idx == 6) {
- return 7;
- }
- else if (idx == 7) {
- return 8;
- }
- else if (idx == 8) {
- return 9;
- }
- else if (idx == 9) {
- return 10;
- }
- else if (idx == 10) {
- return 11;
- }
- else if (idx == 11) {
- return 12;
- }
- else if (idx == 12) {
- return 13;
- }
- else if (idx == 13) {
- return 14;
- }
- else if (idx == 14) {
- return 15;
- }
- else if (idx == 15) {
- return 16;
- }
- else if (idx == 16) {
- return 17;
- }
- else if (idx == 17) {
- return 18;
- }
- else if (idx == 18) {
- return 19;
- }
- else if (idx == 19) {
- return 20;
- }
- else if (idx == 20) {
- return 21;
- }
- else if (idx == 21) {
- return 22;
- }
- else if (idx == 22) {
- return 23;
- }
- else if (idx == 23) {
- return 24;
- }
- else if (idx == 24) {
- return 25;
- }
- else if (idx == 25) {
- return 26;
- }
- else if (idx == 26) {
- return 27;
- }
- else if (idx == 27) {
- return 28;
- }
- else if (idx == 28) {
- return 29;
- }
- else if (idx == 29) {
- return 30;
- }
- else if (idx == 30) {
- return 31;
- }
- else if (idx == 31) {
- return 32;
- }
- else if (idx == 32) {
- return 33;
- }
- else if (idx == 33) {
- return 34;
- }
- else if (idx == 34) {
- return 35;
- }
- else if (idx == 35) {
- return 36;
- }
- else if (idx == 36) {
- return 37;
- }
- else if (idx == 37) {
- return 38;
- }
- else if (idx == 38) {
- return 39;
- }
- else if (idx == 39) {
- return 40;
- }
- else if (idx == 40) {
- return 41;
- }
- else if (idx == 41) {
- return 42;
- }
- else if (idx == 42) {
- return 43;
- }
- else if (idx == 43) {
- return 44;
- }
- else if (idx == 44) {
- return 45;
- }
- else if (idx == 45) {
- return 46;
- }
- else if (idx == 46) {
- return 47;
- }
- else if (idx == 47) {
- return 48;
- }
- else if (idx == 48) {
- return 49;
- }
- else if (idx == 49) {
- return 50;
- }
- else if (idx == 50) {
- return 51;
- }
- else if (idx == 51) {
- return 52;
- }
- else if (idx == 52) {
- return 53;
- }
- else if (idx == 53) {
- return 54;
- }
- else if (idx == 54) {
- return 55;
- }
- else if (idx == 55) {
- return 56;
- }
- else if (idx == 56) {
- return 57;
- }
- else if (idx == 57) {
- return 58;
- }
- else if (idx == 58) {
- return 59;
- }
- else if (idx == 59) {
- return 60;
- }
- else if (idx == 60) {
- return 61;
- }
- else if (idx == 61) {
- return 62;
- }
- else if (idx == 62) {
- return 63;
- }
- else if (idx == 63) {
- return 64;
- }
- else if (idx == 64) {
- return 65;
- }
- else if (idx == 65) {
- return 66;
- }
- else if (idx == 66) {
- return 67;
- }
- else if (idx == 67) {
- return 68;
- }
- else if (idx == 68) {
- return 69;
- }
- else if (idx == 69) {
- return 70;
- }
- else if (idx == 70) {
- return 71;
- }
- else if (idx == 71) {
- return 72;
- }
- else if (idx == 72) {
- return 73;
- }
- else if (idx == 73) {
- return 74;
- }
- else if (idx == 74) {
- return 75;
- }
- else if (idx == 75) {
- return 76;
- }
- else if (idx == 76) {
- return 77;
- }
- else if (idx == 77) {
- return 78;
- }
- else if (idx == 78) {
- return 79;
- }
- else if (idx == 79) {
- return 80;
- }
- else if (idx == 80) {
- return 81;
- }
- else if (idx == 81) {
- return 82;
- }
- else if (idx == 82) {
- return 83;
- }
- else if (idx == 83) {
- return 84;
- }
- else if (idx == 84) {
- return 85;
- }
- else if (idx == 85) {
- return 86;
- }
- else if (idx == 86) {
- return 87;
- }
- else if (idx == 87) {
- return 88;
- }
- else if (idx == 88) {
- return 89;
- }
- else if (idx == 89) {
- return 90;
- }
- else if (idx == 90) {
- return 91;
- }
- else if (idx == 91) {
- return 92;
- }
- else if (idx == 92) {
- return 93;
- }
- else if (idx == 93) {
- return 94;
- }
- else if (idx == 94) {
- return 95;
- }
- else if (idx == 95) {
- return 96;
- }
- else if (idx == 96) {
- return 97;
- }
- else if (idx == 97) {
- return 98;
- }
- else if (idx == 98) {
- return 99;
- }
- else if (idx == 99) {
- return 100;
- }
- else if (idx == 100) {
- return 101;
- }
- else if (idx == 101) {
- return 102;
- }
- else if (idx == 102) {
- return 103;
- }
- else if (idx == 103) {
- return 104;
- }
- else if (idx == 104) {
- return 105;
- }
- else if (idx == 105) {
- return 106;
- }
- else if (idx == 106) {
- return 107;
- }
- else if (idx == 107) {
- return 108;
- }
- else if (idx == 108) {
- return 109;
- }
- else if (idx == 109) {
- return 110;
- }
- else if (idx == 110) {
- return 111;
- }
- else if (idx == 111) {
- return 112;
- }
- else if (idx == 112) {
- return 113;
- }
- else if (idx == 113) {
- return 114;
- }
- else if (idx == 114) {
- return 115;
- }
- else if (idx == 115) {
- return 116;
- }
- else if (idx == 116) {
- return 117;
- }
- else if (idx == 117) {
- return 118;
- }
- else if (idx == 118) {
- return 119;
- }
- else if (idx == 119) {
- return 120;
- }
- else if (idx == 120) {
- return 121;
- }
- else if (idx == 121) {
- return 122;
- }
- else if (idx == 122) {
- return 123;
- }
- else if (idx == 123) {
- return 124;
- }
- else if (idx == 124) {
- return 125;
- }
- else if (idx == 125) {
- return 126;
- }
- else if (idx == 126) {
- return 127;
- }
- else {
- return 0;
- }
-}
-
-
-
-/* --------------------- sifive_gpio0 ------------ */
-
-
-/* --------------------- sifive_gpio_button ------------ */
-
-
-/* --------------------- sifive_gpio_led ------------ */
-
-
-/* --------------------- sifive_gpio_switch ------------ */
-
-
-/* --------------------- sifive_spi0 ------------ */
-
-
-/* --------------------- sifive_test0 ------------ */
-static inline unsigned long __metal_driver_sifive_test0_base( )
-{
- return 16384;
-}
-
-static inline unsigned long __metal_driver_sifive_test0_size( )
-{
- return 4096;
-}
-
-
-
-/* --------------------- sifive_uart0 ------------ */
-
-
-/* --------------------- sifive_fe310_g000_hfrosc ------------ */
-
-
-/* --------------------- sifive_fe310_g000_hfxosc ------------ */
-
-
-/* --------------------- sifive_fe310_g000_pll ------------ */
-
-
-/* --------------------- sifive_fe310_g000_prci ------------ */
-
-
-/* --------------------- sifive_fu540_c000_l2 ------------ */
-
-
-#define __METAL_DT_MAX_MEMORIES 7
-
-asm (".weak __metal_memory_table");
-struct metal_memory *__metal_memory_table[] = {
- &__metal_dt_mem_dtim_1000000,
- &__metal_dt_mem_itim_1800000,
- &__metal_dt_mem_itim_1808000,
- &__metal_dt_mem_itim_1810000,
- &__metal_dt_mem_itim_1818000,
- &__metal_dt_mem_itim_1820000,
- &__metal_dt_mem_memory_80000000};
-
-/* From clint@2000000 */
-#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller)
-
-#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller)
-
-#define __METAL_DT_MAX_HARTS 5
-
-asm (".weak __metal_cpu_table");
-struct __metal_driver_cpu *__metal_cpu_table[] = {
- &__metal_dt_cpu_0,
- &__metal_dt_cpu_1,
- &__metal_dt_cpu_2,
- &__metal_dt_cpu_3,
- &__metal_dt_cpu_4};
-
-/* From interrupt_controller@c000000 */
-#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
-
-#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
-
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
-
-/* From global_external_interrupts */
-#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc)
-
-#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc)
-
-#define __MEE_DT_MAX_GPIOS 0
-
-asm (".weak __metal_gpio_table");
-struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = {
- NULL };
-#define __METAL_DT_MAX_BUTTONS 0
-
-asm (".weak __metal_button_table");
-struct __metal_driver_sifive_gpio_button *__metal_button_table[] = {
- NULL };
-#define __METAL_DT_MAX_LEDS 0
-
-asm (".weak __metal_led_table");
-struct __metal_driver_sifive_gpio_led *__metal_led_table[] = {
- NULL };
-#define __METAL_DT_MAX_SWITCHES 0
-
-asm (".weak __metal_switch_table");
-struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = {
- NULL };
-#define __METAL_DT_MAX_SPIS 0
-
-asm (".weak __metal_spi_table");
-struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
- NULL };
-/* From teststatus@4000 */
-#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown)
-
-#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown)
-
-/* From cache_controller@2010000 */
-#define __METAL_DT_SIFIVE_FU540_C000_L2_HANDLE (&__metal_dt_cache_controller_2010000)
-
-#define __METAL_DT_CACHE_CONTROLLER_2010000_HANDLE (&__metal_dt_cache_controller_2010000)
-
-#endif /* MACROS_ELSE_COREIP_U54MC_RTL__METAL_H*/
-
-#endif /* ! __METAL_MACHINE_MACROS */
-
-#endif /* ! ASSEMBLY */
diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
deleted file mode 100644
index 88d7a5e..0000000
--- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-OUTPUT_ARCH("riscv")
-
-ENTRY(_enter)
-
-MEMORY
-{
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
- itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- itim_init PT_LOAD;
- ram PT_LOAD;
- itim PT_LOAD;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
- PROVIDE(__stack_size = __stack_size);
- __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
- PROVIDE(__metal_boot_hart = 0);
- PROVIDE(__metal_chicken_bit = 0);
-
-
- .init :
- {
- KEEP (*(.text.metal.init.enter))
- KEEP (*(SORT_NONE(.init)))
- KEEP (*(.text.libgloss.start))
- } >ram AT>ram :ram
-
-
-
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >ram AT>ram :ram
-
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
-
-
-
- . = ALIGN(4);
-
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >ram AT>ram :ram
-
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >ram AT>ram :ram
-
-
- .finit_array :
- {
- PROVIDE_HIDDEN (__finit_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__finit_array_end = .);
- } >ram AT>ram :ram
-
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >ram AT>ram :ram
-
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >ram AT>ram :ram
-
-
- .litimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_source_start = . );
- } >ram AT>ram :ram
-
-
- .ditimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_target_start = . );
- } >itim AT>ram :itim_init
-
-
- .itim :
- {
- *(.itim .itim.*)
- } >itim AT>ram :itim_init
-
-
- . = ALIGN(8);
- PROVIDE( metal_segment_itim_target_end = . );
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >ram AT>ram :ram
-
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- PROVIDE( metal_segment_data_source_start = . );
- } >ram AT>ram :ram
-
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_data_target_start = . );
- } >ram AT>ram :ram_init
-
-
- .data :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.* .sdata2.*)
- *(.gnu.linkonce.s.*)
- } >ram AT>ram :ram_init
-
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
- PROVIDE( metal_segment_data_target_end = . );
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- PROVIDE( metal_segment_bss_target_start = . );
-
-
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
- PROVIDE( metal_segment_bss_target_end = . );
-
-
- .stack :
- {
- PROVIDE(metal_segment_stack_begin = .);
- . = __stack_size;
- PROVIDE( _sp = . );
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- PROVIDE(metal_segment_stack_end = .);
- } >ram AT>ram :ram
-
-
- .heap :
- {
- PROVIDE( metal_segment_heap_target_start = . );
- . = __heap_size;
- PROVIDE( metal_segment_heap_target_end = . );
- PROVIDE( _heap_end = . );
- } >ram AT>ram :ram
-
-
-}
-
diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
deleted file mode 100644
index 3b03685..0000000
--- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Copyright 2019 SiFive, Inc */
-/* SPDX-License-Identifier: Apache-2.0 */
-/* ----------------------------------- */
-/* ----------------------------------- */
-
-OUTPUT_ARCH("riscv")
-
-ENTRY(_enter)
-
-MEMORY
-{
- ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000
- itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000
-}
-
-PHDRS
-{
- flash PT_LOAD;
- ram_init PT_LOAD;
- itim_init PT_LOAD;
- ram PT_LOAD;
- itim PT_LOAD;
-}
-
-SECTIONS
-{
- __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
- PROVIDE(__stack_size = __stack_size);
- __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
- PROVIDE(__metal_boot_hart = 0);
- PROVIDE(__metal_chicken_bit = 0);
-
-
- .init :
- {
- KEEP (*(.text.metal.init.enter))
- KEEP (*(SORT_NONE(.init)))
- KEEP (*(.text.libgloss.start))
- } >ram AT>ram :ram
-
-
- .text :
- {
- *(.text.unlikely .text.unlikely.*)
- *(.text.startup .text.startup.*)
- *(.text .text.*)
- *(.gnu.linkonce.t.*)
- } >ram AT>ram :ram
-
-
- .fini :
- {
- KEEP (*(SORT_NONE(.fini)))
- } >ram AT>ram :ram
-
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
-
- .rodata :
- {
- *(.rdata)
- *(.rodata .rodata.*)
- *(.gnu.linkonce.r.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- } >ram AT>ram :ram
-
-
- . = ALIGN(4);
-
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >ram AT>ram :ram
-
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >ram AT>ram :ram
-
-
- .finit_array :
- {
- PROVIDE_HIDDEN (__finit_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__finit_array_end = .);
- } >ram AT>ram :ram
-
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >ram AT>ram :ram
-
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >ram AT>ram :ram
-
-
- .litimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_source_start = . );
- } >ram AT>ram :ram
-
-
- .ditimalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_itim_target_start = . );
- } >itim AT>ram :itim_init
-
-
- .itim :
- {
- *(.itim .itim.*)
- } >itim AT>ram :itim_init
-
-
- . = ALIGN(8);
- PROVIDE( metal_segment_itim_target_end = . );
-
-
- .lalign :
- {
- . = ALIGN(4);
- PROVIDE( _data_lma = . );
- PROVIDE( metal_segment_data_source_start = . );
- } >ram AT>ram :ram
-
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE( metal_segment_data_target_start = . );
- } >ram AT>ram :ram_init
-
-
- .data :
- {
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.* .sdata2.*)
- *(.gnu.linkonce.s.*)
- } >ram AT>ram :ram_init
-
-
- . = ALIGN(4);
- PROVIDE( _edata = . );
- PROVIDE( edata = . );
- PROVIDE( metal_segment_data_target_end = . );
- PROVIDE( _fbss = . );
- PROVIDE( __bss_start = . );
- PROVIDE( metal_segment_bss_target_start = . );
-
-
- .bss :
- {
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss .bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- . = ALIGN(4);
- } >ram AT>ram :ram
-
-
- . = ALIGN(8);
- PROVIDE( _end = . );
- PROVIDE( end = . );
- PROVIDE( metal_segment_bss_target_end = . );
-
-
- .stack :
- {
- PROVIDE(metal_segment_stack_begin = .);
- . = __stack_size;
- PROVIDE( _sp = . );
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- . = __stack_size;
- PROVIDE(metal_segment_stack_end = .);
- } >ram AT>ram :ram
-
-
- .heap :
- {
- PROVIDE( metal_segment_heap_target_start = . );
- . = __heap_size;
- PROVIDE( metal_segment_heap_target_end = . );
- PROVIDE( _heap_end = . );
- } >ram AT>ram :ram
-
-
-}
-
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
deleted file mode 100644
index cbd21b4..0000000
--- a/bsp/coreip-u54mc-rtl/settings.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright 2019 SiFive, Inc #
-# SPDX-License-Identifier: Apache-2.0 #
-# ----------------------------------- #
-# ----------------------------------- #
-
-RISCV_ARCH=rv64imac
-RISCV_ABI=lp64
-RISCV_CMODEL=medany
-RISCV_SERIES=sifive-5-series
-
-COREIP_MEM_WIDTH=128
-
-TARGET_TAGS=rtl
-TARGET_DHRY_ITERS=2000
-TARGET_CORE_ITERS=5
generated by cgit v1.2.1-18-gbd029 (git 2.20.0) at 2024-05-10 09:27:51 +0000