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-rw-r--r--bsp/coreip-u54mc-rtl/design.dts3
-rw-r--r--bsp/coreip-u54mc-rtl/metal-inline.h3
-rw-r--r--bsp/coreip-u54mc-rtl/metal-platform.h2
-rw-r--r--bsp/coreip-u54mc-rtl/metal.default.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/metal.h24
-rw-r--r--bsp/coreip-u54mc-rtl/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/settings.mk3
8 files changed, 37 insertions, 7 deletions
diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts
index beba177..2982dd5 100644
--- a/bsp/coreip-u54mc-rtl/design.dts
+++ b/bsp/coreip-u54mc-rtl/design.dts
@@ -5,6 +5,9 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev";
model = "SiFive,FU540G";
+ chosen {
+ metal,boothart = <&L13>;
+ };
L36: cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h
index 62b9eb9..34e4d33 100644
--- a/bsp/coreip-u54mc-rtl/metal-inline.h
+++ b/bsp/coreip-u54mc-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -27,6 +27,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu);
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h
index 0919ca3..7045d23 100644
--- a/bsp/coreip-u54mc-rtl/metal-platform.h
+++ b/bsp/coreip-u54mc-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H
diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds
index 32ee163..a95cc07 100644
--- a/bsp/coreip-u54mc-rtl/metal.default.lds
+++ b/bsp/coreip-u54mc-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -28,6 +28,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 1);
.init :
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
index f60e70c..417332f 100644
--- a/bsp/coreip-u54mc-rtl/metal.h
+++ b/bsp/coreip-u54mc-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -249,6 +249,28 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 0;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 0;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+ return 1;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+ return 2;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+ return 3;
+ }
+ else {
+ return -1;
+ }
+}
+
static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
{
if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
index 6a59904..b5f35f7 100644
--- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -28,6 +28,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 1);
.init :
diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
index 32ee163..a95cc07 100644
--- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-35 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -28,6 +28,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 1);
.init :
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
index 4509247..ae9e038 100644
--- a/bsp/coreip-u54mc-rtl/settings.mk
+++ b/bsp/coreip-u54mc-rtl/settings.mk
@@ -1,7 +1,7 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 21-05-2019 10-54-35 #
+# [XXXXX] 23-05-2019 13-29-49 #
# ----------------------------------- #
RISCV_ARCH=rv64imac
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
COREIP_MEM_WIDTH=128
TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 06:00:09 +0000