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-rw-r--r--bsp/coreip-u54mc-rtl/metal-inline.h2
-rw-r--r--bsp/coreip-u54mc-rtl/metal-platform.h2
-rw-r--r--bsp/coreip-u54mc-rtl/metal.default.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/metal.h14
-rw-r--r--bsp/coreip-u54mc-rtl/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-u54mc-rtl/settings.mk8
7 files changed, 20 insertions, 15 deletions
diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h
index 34e4d33..ca4fc82 100644
--- a/bsp/coreip-u54mc-rtl/metal-inline.h
+++ b/bsp/coreip-u54mc-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
#ifndef ASSEMBLY
diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h
index 7045d23..332c8bb 100644
--- a/bsp/coreip-u54mc-rtl/metal-platform.h
+++ b/bsp/coreip-u54mc-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
#ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H
diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds
index a95cc07..1476969 100644
--- a/bsp/coreip-u54mc-rtl/metal.default.lds
+++ b/bsp/coreip-u54mc-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 1);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h
index 417332f..f1fa821 100644
--- a/bsp/coreip-u54mc-rtl/metal.h
+++ b/bsp/coreip-u54mc-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -69,13 +69,13 @@
#include <metal/drivers/fixed-clock.h>
#include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
#include <metal/pmp.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,test0.h>
-#include <metal/drivers/sifive,fu540-c000,l2.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_test0.h>
+#include <metal/drivers/sifive_fu540-c000_l2.h>
struct metal_memory __metal_dt_mem_dtim_1000000;
diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
index b5f35f7..532321d 100644
--- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 1);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
index a95cc07..1476969 100644
--- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-06-13 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 1);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
index ae9e038..c751abc 100644
--- a/bsp/coreip-u54mc-rtl/settings.mk
+++ b/bsp/coreip-u54mc-rtl/settings.mk
@@ -1,14 +1,16 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49 #
+# [XXXXX] 28-05-2019 10-06-13 #
# ----------------------------------- #
-RISCV_ARCH=rv64imac
-RISCV_ABI=lp64
+RISCV_ARCH=rv64imafdc
+RISCV_ABI=lp64d
RISCV_CMODEL=medany
+RISCV_SERIES=sifive-5-series
COREIP_MEM_WIDTH=128
TARGET_TAGS=rtl
TARGET_DHRY_ITERS=2000
+TARGET_CORE_ITERS=5