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-rw-r--r--bsp/env/freedom-e300-hifive1/entry.S138
-rw-r--r--bsp/env/freedom-e300-hifive1/start.S115
2 files changed, 111 insertions, 142 deletions
diff --git a/bsp/env/freedom-e300-hifive1/entry.S b/bsp/env/freedom-e300-hifive1/entry.S
index 3eb2638..cbf26eb 100644
--- a/bsp/env/freedom-e300-hifive1/entry.S
+++ b/bsp/env/freedom-e300-hifive1/entry.S
@@ -1,55 +1,47 @@
-// See LICENSE for License Details
+// See LICENSE for license details
+
#ifndef ENTRY_S
#define ENTRY_S
#include "encoding.h"
-
-#if XLEN == 64
-# define LREG ld
-# define SREG sd
-# define REGBYTES 8
-#else
-# define LREG lw
-# define SREG sw
-# define REGBYTES 4
-#endif
+#include "sifive/bits.h"
.section .text.entry
.global trap_entry
trap_entry:
addi sp, sp, -32*REGBYTES
- SREG x1, 1*REGBYTES(sp)
- SREG x2, 2*REGBYTES(sp)
- SREG x3, 3*REGBYTES(sp)
- SREG x4, 4*REGBYTES(sp)
- SREG x5, 5*REGBYTES(sp)
- SREG x6, 6*REGBYTES(sp)
- SREG x7, 7*REGBYTES(sp)
- SREG x8, 8*REGBYTES(sp)
- SREG x9, 9*REGBYTES(sp)
- SREG x10, 10*REGBYTES(sp)
- SREG x11, 11*REGBYTES(sp)
- SREG x12, 12*REGBYTES(sp)
- SREG x13, 13*REGBYTES(sp)
- SREG x14, 14*REGBYTES(sp)
- SREG x15, 15*REGBYTES(sp)
- SREG x16, 16*REGBYTES(sp)
- SREG x17, 17*REGBYTES(sp)
- SREG x18, 18*REGBYTES(sp)
- SREG x19, 19*REGBYTES(sp)
- SREG x20, 20*REGBYTES(sp)
- SREG x21, 21*REGBYTES(sp)
- SREG x22, 22*REGBYTES(sp)
- SREG x23, 23*REGBYTES(sp)
- SREG x24, 24*REGBYTES(sp)
- SREG x25, 25*REGBYTES(sp)
- SREG x26, 26*REGBYTES(sp)
- SREG x27, 27*REGBYTES(sp)
- SREG x28, 28*REGBYTES(sp)
- SREG x29, 29*REGBYTES(sp)
- SREG x30, 30*REGBYTES(sp)
- SREG x31, 31*REGBYTES(sp)
+ STORE x1, 1*REGBYTES(sp)
+ STORE x2, 2*REGBYTES(sp)
+ STORE x3, 3*REGBYTES(sp)
+ STORE x4, 4*REGBYTES(sp)
+ STORE x5, 5*REGBYTES(sp)
+ STORE x6, 6*REGBYTES(sp)
+ STORE x7, 7*REGBYTES(sp)
+ STORE x8, 8*REGBYTES(sp)
+ STORE x9, 9*REGBYTES(sp)
+ STORE x10, 10*REGBYTES(sp)
+ STORE x11, 11*REGBYTES(sp)
+ STORE x12, 12*REGBYTES(sp)
+ STORE x13, 13*REGBYTES(sp)
+ STORE x14, 14*REGBYTES(sp)
+ STORE x15, 15*REGBYTES(sp)
+ STORE x16, 16*REGBYTES(sp)
+ STORE x17, 17*REGBYTES(sp)
+ STORE x18, 18*REGBYTES(sp)
+ STORE x19, 19*REGBYTES(sp)
+ STORE x20, 20*REGBYTES(sp)
+ STORE x21, 21*REGBYTES(sp)
+ STORE x22, 22*REGBYTES(sp)
+ STORE x23, 23*REGBYTES(sp)
+ STORE x24, 24*REGBYTES(sp)
+ STORE x25, 25*REGBYTES(sp)
+ STORE x26, 26*REGBYTES(sp)
+ STORE x27, 27*REGBYTES(sp)
+ STORE x28, 28*REGBYTES(sp)
+ STORE x29, 29*REGBYTES(sp)
+ STORE x30, 30*REGBYTES(sp)
+ STORE x31, 31*REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
@@ -61,37 +53,37 @@ trap_entry:
li t0, MSTATUS_MPP
csrs mstatus, t0
- LREG x1, 1*REGBYTES(sp)
- LREG x2, 2*REGBYTES(sp)
- LREG x3, 3*REGBYTES(sp)
- LREG x4, 4*REGBYTES(sp)
- LREG x5, 5*REGBYTES(sp)
- LREG x6, 6*REGBYTES(sp)
- LREG x7, 7*REGBYTES(sp)
- LREG x8, 8*REGBYTES(sp)
- LREG x9, 9*REGBYTES(sp)
- LREG x10, 10*REGBYTES(sp)
- LREG x11, 11*REGBYTES(sp)
- LREG x12, 12*REGBYTES(sp)
- LREG x13, 13*REGBYTES(sp)
- LREG x14, 14*REGBYTES(sp)
- LREG x15, 15*REGBYTES(sp)
- LREG x16, 16*REGBYTES(sp)
- LREG x17, 17*REGBYTES(sp)
- LREG x18, 18*REGBYTES(sp)
- LREG x19, 19*REGBYTES(sp)
- LREG x20, 20*REGBYTES(sp)
- LREG x21, 21*REGBYTES(sp)
- LREG x22, 22*REGBYTES(sp)
- LREG x23, 23*REGBYTES(sp)
- LREG x24, 24*REGBYTES(sp)
- LREG x25, 25*REGBYTES(sp)
- LREG x26, 26*REGBYTES(sp)
- LREG x27, 27*REGBYTES(sp)
- LREG x28, 28*REGBYTES(sp)
- LREG x29, 29*REGBYTES(sp)
- LREG x30, 30*REGBYTES(sp)
- LREG x31, 31*REGBYTES(sp)
+ LOAD x1, 1*REGBYTES(sp)
+ LOAD x2, 2*REGBYTES(sp)
+ LOAD x3, 3*REGBYTES(sp)
+ LOAD x4, 4*REGBYTES(sp)
+ LOAD x5, 5*REGBYTES(sp)
+ LOAD x6, 6*REGBYTES(sp)
+ LOAD x7, 7*REGBYTES(sp)
+ LOAD x8, 8*REGBYTES(sp)
+ LOAD x9, 9*REGBYTES(sp)
+ LOAD x10, 10*REGBYTES(sp)
+ LOAD x11, 11*REGBYTES(sp)
+ LOAD x12, 12*REGBYTES(sp)
+ LOAD x13, 13*REGBYTES(sp)
+ LOAD x14, 14*REGBYTES(sp)
+ LOAD x15, 15*REGBYTES(sp)
+ LOAD x16, 16*REGBYTES(sp)
+ LOAD x17, 17*REGBYTES(sp)
+ LOAD x18, 18*REGBYTES(sp)
+ LOAD x19, 19*REGBYTES(sp)
+ LOAD x20, 20*REGBYTES(sp)
+ LOAD x21, 21*REGBYTES(sp)
+ LOAD x22, 22*REGBYTES(sp)
+ LOAD x23, 23*REGBYTES(sp)
+ LOAD x24, 24*REGBYTES(sp)
+ LOAD x25, 25*REGBYTES(sp)
+ LOAD x26, 26*REGBYTES(sp)
+ LOAD x27, 27*REGBYTES(sp)
+ LOAD x28, 28*REGBYTES(sp)
+ LOAD x29, 29*REGBYTES(sp)
+ LOAD x30, 30*REGBYTES(sp)
+ LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
diff --git a/bsp/env/freedom-e300-hifive1/start.S b/bsp/env/freedom-e300-hifive1/start.S
index c8ec662..2388ec0 100644
--- a/bsp/env/freedom-e300-hifive1/start.S
+++ b/bsp/env/freedom-e300-hifive1/start.S
@@ -1,81 +1,58 @@
-/*-
- * Copyright (c) 2013-2015 Marko Zec, University of Zagreb
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $Id$
- */
-
-/*
- * Copy data, clear BSS, set small data index register and jump into main().
- *
- * Assumes that the loader has already properly:
- * 1) set stack pointer
- * 2) set return address
- * 3) invalidated caches
- */
+// See LICENSE for license details.
.section .init
.globl _start
.type _start,@function
_start:
- la gp, _gp
- la sp, _sp
-
- /* Load data sections */
- la s0, _data
- la s1, _edata
- la s2, _data_lma
- j 2f
+ la gp, _gp
+ la sp, _sp
+
+ /* Load data section */
+ la a0, _data_lma
+ la a1, _data
+ la a2, _edata
+ bgeu a1, a2, 2f
1:
- lw t0, (s2)
- sw t0, (s0)
- addi s2, s2, 4
- addi s0, s0, 4
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, 1b
2:
- bltu s0, s1, 1b
- la s1, _end /* End of BSS section, word aligned */
- la s0, __bss_start /* Start of BSS section, word aligned */
- j bss_bzero_enter
+ /* Clear bss section */
+ la a0, __bss_start
+ la a1, _end
+ bgeu a0, a1, 2f
+1:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, 1b
+2:
- /* The loader doesn't bzero the BSS, so we must do it here. */
-bss_bzero_loop:
- sw zero, (s0)
- addi s0, s0, 4
-bss_bzero_enter:
- bne s0, s1, bss_bzero_loop
+ /* Call global constructors */
+ la a0, __libc_fini_array
+ call atexit
+ call __libc_init_array
+
+#ifndef __riscv_float_abi_soft
+ /* Enable FPU */
+ li t0, MSTATUS_FS
+ csrs mstatus, t0
+ csrr t1, mstatus
+ and t1, t1, t0
+ beqz t1, 1f
+ fssr x0
+1:
+#endif
- la s0, __init_array_start
- la s1, __init_array_end
- move s2, ra
- j ctor_loop_enter
+ call main
+ tail exit
-ctor_loop:
- lw a0, (s0)
- addi s0, s0, 4
- jalr a0
-ctor_loop_enter:
- bne s0, s1, ctor_loop
- move ra, s2
- j _init
+ /* init_array/fini_array are used instead */
+ .globl _init
+ .globl _fini
+_init:
+_fini:
+ ret
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 03:16:28 +0000