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-rw-r--r--bsp/env/common.mk1
-rw-r--r--bsp/env/freedom-e300-arty/init.c3
l---------bsp/env/freedom-e300-arty/start.S1
-rw-r--r--bsp/env/freedom-e300-hifive1/entry.S167
-rw-r--r--bsp/env/freedom-e300-hifive1/init.c3
-rw-r--r--bsp/env/freedom-e300-hifive1/start.S81
6 files changed, 181 insertions, 75 deletions
diff --git a/bsp/env/common.mk b/bsp/env/common.mk
index 42c0f96..8d91805 100644
--- a/bsp/env/common.mk
+++ b/bsp/env/common.mk
@@ -4,6 +4,7 @@ BOARD ?= freedom-e300-hifive1
ENV_DIR = $(BSP_BASE)/env
PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
+ASM_SRCS += $(PLATFORM_DIR)/start.S
ASM_SRCS += $(PLATFORM_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
C_SRCS += $(ENV_DIR)/syscall.c
diff --git a/bsp/env/freedom-e300-arty/init.c b/bsp/env/freedom-e300-arty/init.c
index 36272f7..4313808 100644
--- a/bsp/env/freedom-e300-arty/init.c
+++ b/bsp/env/freedom-e300-arty/init.c
@@ -5,6 +5,7 @@
#include "encoding.h"
extern int main(int argc, char** argv);
+extern void trap_entry();
uint32_t get_cpu_freq()
{
@@ -55,7 +56,7 @@ void _init()
printf("core freq at %d Hz\n", get_cpu_freq());
- write_csr(mtvec, &handle_trap);
+ write_csr(mtvec, &trap_entry);
_exit(main(0, NULL));
}
diff --git a/bsp/env/freedom-e300-arty/start.S b/bsp/env/freedom-e300-arty/start.S
new file mode 120000
index 0000000..028e9bf
--- /dev/null
+++ b/bsp/env/freedom-e300-arty/start.S
@@ -0,0 +1 @@
+../freedom-e300-hifive1/start.S \ No newline at end of file
diff --git a/bsp/env/freedom-e300-hifive1/entry.S b/bsp/env/freedom-e300-hifive1/entry.S
index c8ec662..524f8ee 100644
--- a/bsp/env/freedom-e300-hifive1/entry.S
+++ b/bsp/env/freedom-e300-hifive1/entry.S
@@ -1,81 +1,102 @@
-/*-
- * Copyright (c) 2013-2015 Marko Zec, University of Zagreb
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $Id$
- */
+#ifndef ENTRY_S
+#define ENTRY_S
-/*
- * Copy data, clear BSS, set small data index register and jump into main().
- *
- * Assumes that the loader has already properly:
- * 1) set stack pointer
- * 2) set return address
- * 3) invalidated caches
- */
+#include "encoding.h"
- .section .init
- .globl _start
- .type _start,@function
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
-_start:
- la gp, _gp
- la sp, _sp
+ .section .text.entry
+ .global trap_entry
+trap_entry:
+ addi sp, sp, -32*REGBYTES
- /* Load data sections */
- la s0, _data
- la s1, _edata
- la s2, _data_lma
- j 2f
-1:
- lw t0, (s2)
- sw t0, (s0)
- addi s2, s2, 4
- addi s0, s0, 4
-2:
- bltu s0, s1, 1b
+ SREG x1, 1*REGBYTES(sp)
+ SREG x2, 2*REGBYTES(sp)
+ SREG x3, 3*REGBYTES(sp)
+ SREG x4, 4*REGBYTES(sp)
+ SREG x5, 5*REGBYTES(sp)
+ SREG x6, 6*REGBYTES(sp)
+ SREG x7, 7*REGBYTES(sp)
+ SREG x8, 8*REGBYTES(sp)
+ SREG x9, 9*REGBYTES(sp)
+ SREG x10, 10*REGBYTES(sp)
+ SREG x11, 11*REGBYTES(sp)
+ SREG x12, 12*REGBYTES(sp)
+ SREG x13, 13*REGBYTES(sp)
+ SREG x14, 14*REGBYTES(sp)
+ SREG x15, 15*REGBYTES(sp)
+ SREG x16, 16*REGBYTES(sp)
+ SREG x17, 17*REGBYTES(sp)
+ SREG x18, 18*REGBYTES(sp)
+ SREG x19, 19*REGBYTES(sp)
+ SREG x20, 20*REGBYTES(sp)
+ SREG x21, 21*REGBYTES(sp)
+ SREG x22, 22*REGBYTES(sp)
+ SREG x23, 23*REGBYTES(sp)
+ SREG x24, 24*REGBYTES(sp)
+ SREG x25, 25*REGBYTES(sp)
+ SREG x26, 26*REGBYTES(sp)
+ SREG x27, 27*REGBYTES(sp)
+ SREG x28, 28*REGBYTES(sp)
+ SREG x29, 29*REGBYTES(sp)
+ SREG x30, 30*REGBYTES(sp)
+ SREG x31, 31*REGBYTES(sp)
- la s1, _end /* End of BSS section, word aligned */
- la s0, __bss_start /* Start of BSS section, word aligned */
- j bss_bzero_enter
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
- /* The loader doesn't bzero the BSS, so we must do it here. */
-bss_bzero_loop:
- sw zero, (s0)
- addi s0, s0, 4
-bss_bzero_enter:
- bne s0, s1, bss_bzero_loop
+ # Remain in M-mode after mret
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
- la s0, __init_array_start
- la s1, __init_array_end
- move s2, ra
- j ctor_loop_enter
+ LREG x1, 1*REGBYTES(sp)
+ LREG x2, 2*REGBYTES(sp)
+ LREG x3, 3*REGBYTES(sp)
+ LREG x4, 4*REGBYTES(sp)
+ LREG x5, 5*REGBYTES(sp)
+ LREG x6, 6*REGBYTES(sp)
+ LREG x7, 7*REGBYTES(sp)
+ LREG x8, 8*REGBYTES(sp)
+ LREG x9, 9*REGBYTES(sp)
+ LREG x10, 10*REGBYTES(sp)
+ LREG x11, 11*REGBYTES(sp)
+ LREG x12, 12*REGBYTES(sp)
+ LREG x13, 13*REGBYTES(sp)
+ LREG x14, 14*REGBYTES(sp)
+ LREG x15, 15*REGBYTES(sp)
+ LREG x16, 16*REGBYTES(sp)
+ LREG x17, 17*REGBYTES(sp)
+ LREG x18, 18*REGBYTES(sp)
+ LREG x19, 19*REGBYTES(sp)
+ LREG x20, 20*REGBYTES(sp)
+ LREG x21, 21*REGBYTES(sp)
+ LREG x22, 22*REGBYTES(sp)
+ LREG x23, 23*REGBYTES(sp)
+ LREG x24, 24*REGBYTES(sp)
+ LREG x25, 25*REGBYTES(sp)
+ LREG x26, 26*REGBYTES(sp)
+ LREG x27, 27*REGBYTES(sp)
+ LREG x28, 28*REGBYTES(sp)
+ LREG x29, 29*REGBYTES(sp)
+ LREG x30, 30*REGBYTES(sp)
+ LREG x31, 31*REGBYTES(sp)
-ctor_loop:
- lw a0, (s0)
- addi s0, s0, 4
- jalr a0
-ctor_loop_enter:
- bne s0, s1, ctor_loop
- move ra, s2
- j _init
+ addi sp, sp, 32*REGBYTES
+ mret
+
+.weak handle_trap
+handle_trap:
+ j handle_trap
+
+#endif
diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c
index 343f071..05faeea 100644
--- a/bsp/env/freedom-e300-hifive1/init.c
+++ b/bsp/env/freedom-e300-hifive1/init.c
@@ -7,6 +7,7 @@
uint32_t cpu_freq = 0;
extern int main(int argc, char** argv);
+extern void trap_entry();
uint32_t mtime_lo(void)
{
@@ -181,7 +182,7 @@ void _init()
printf("core freq at %d Hz\n", get_cpu_freq());
- write_csr(mtvec, &handle_trap);
+ write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
diff --git a/bsp/env/freedom-e300-hifive1/start.S b/bsp/env/freedom-e300-hifive1/start.S
new file mode 100644
index 0000000..c8ec662
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/start.S
@@ -0,0 +1,81 @@
+/*-
+ * Copyright (c) 2013-2015 Marko Zec, University of Zagreb
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $Id$
+ */
+
+/*
+ * Copy data, clear BSS, set small data index register and jump into main().
+ *
+ * Assumes that the loader has already properly:
+ * 1) set stack pointer
+ * 2) set return address
+ * 3) invalidated caches
+ */
+
+ .section .init
+ .globl _start
+ .type _start,@function
+
+_start:
+ la gp, _gp
+ la sp, _sp
+
+ /* Load data sections */
+ la s0, _data
+ la s1, _edata
+ la s2, _data_lma
+ j 2f
+1:
+ lw t0, (s2)
+ sw t0, (s0)
+ addi s2, s2, 4
+ addi s0, s0, 4
+2:
+ bltu s0, s1, 1b
+
+ la s1, _end /* End of BSS section, word aligned */
+ la s0, __bss_start /* Start of BSS section, word aligned */
+ j bss_bzero_enter
+
+ /* The loader doesn't bzero the BSS, so we must do it here. */
+bss_bzero_loop:
+ sw zero, (s0)
+ addi s0, s0, 4
+bss_bzero_enter:
+ bne s0, s1, bss_bzero_loop
+
+ la s0, __init_array_start
+ la s1, __init_array_end
+ move s2, ra
+ j ctor_loop_enter
+
+ctor_loop:
+ lw a0, (s0)
+ addi s0, s0, 4
+ jalr a0
+ctor_loop_enter:
+ bne s0, s1, ctor_loop
+ move ra, s2
+ j _init
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