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-rw-r--r--bsp/qemu-sifive-s51/README.md2
1 files changed, 2 insertions, 0 deletions
diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md
index 64593f3..7825a98 100644
--- a/bsp/qemu-sifive-s51/README.md
+++ b/bsp/qemu-sifive-s51/README.md
@@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an
- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
- 1 RGB LEDS
+
+This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1