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-rw-r--r--bsp/sifive-hifive-unleashed/design.dts9
-rw-r--r--bsp/sifive-hifive-unleashed/metal-inline.h8
-rw-r--r--bsp/sifive-hifive-unleashed/metal-platform.h15
-rw-r--r--bsp/sifive-hifive-unleashed/metal.default.lds2
-rw-r--r--bsp/sifive-hifive-unleashed/metal.h29
-rw-r--r--bsp/sifive-hifive-unleashed/metal.ramrodata.lds2
-rw-r--r--bsp/sifive-hifive-unleashed/metal.scratchpad.lds2
7 files changed, 41 insertions, 26 deletions
diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts
index ee6897f..8702be3 100644
--- a/bsp/sifive-hifive-unleashed/design.dts
+++ b/bsp/sifive-hifive-unleashed/design.dts
@@ -33,6 +33,7 @@
next-level-cache = <&L24 &L0>;
reg = <0>;
riscv,isa = "rv64imac";
+ riscv,pmpregions = <8>;
sifive,dtim = <&L8>;
sifive,itim = <&L7>;
status = "okay";
@@ -60,6 +61,7 @@
next-level-cache = <&L24 &L0>;
reg = <1>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L11>;
status = "okay";
tlb-split;
@@ -87,6 +89,7 @@
next-level-cache = <&L24 &L0>;
reg = <2>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L14>;
status = "okay";
tlb-split;
@@ -114,6 +117,7 @@
next-level-cache = <&L24 &L0>;
reg = <3>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L17>;
status = "okay";
tlb-split;
@@ -141,6 +145,7 @@
next-level-cache = <&L24 &L0>;
reg = <4>;
riscv,isa = "rv64imafdc";
+ riscv,pmpregions = <8>;
sifive,itim = <&L20>;
status = "okay";
tlb-split;
@@ -160,10 +165,6 @@
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <1>;
- };
refclk: refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h
index 6968bab..6099519 100644
--- a/bsp/sifive-hifive-unleashed/metal-inline.h
+++ b/bsp/sifive-hifive-unleashed/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -33,6 +33,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
/* --------------------- sifive_plic0 ------------ */
@@ -295,11 +296,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
.init_done = 0,
};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
/* From gpio@10060000 */
struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = {
.gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio,
diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h
index 0a1d909..19119c4 100644
--- a/bsp/sifive-hifive-unleashed/metal-platform.h
+++ b/bsp/sifive-hifive-unleashed/metal-platform.h
@@ -1,17 +1,20 @@
+/* Copyright 2019 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+/* ----------------------------------- */
+/* [XXXXX] 21-05-2019 10-54-35 */
+/* ----------------------------------- */
+
#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H
#define SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H
/* From refclk */
#define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL
-#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 33333333UL
#define METAL_FIXED_CLOCK
/* From tlclk */
#define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL
-#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_DIV 2UL
#define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL
-#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_MULT 1UL
#define METAL_FIXED_FACTOR_CLOCK
@@ -43,12 +46,6 @@
#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
#define METAL_RISCV_PLIC0_CLAIM 2097156UL
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
-#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL
-
-#define METAL_RISCV_PMP
-
/* From cache_controller@2010000 */
#define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL
#define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL
diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds
index b4c68be..a0d0420 100644
--- a/bsp/sifive-hifive-unleashed/metal.default.lds
+++ b/bsp/sifive-hifive-unleashed/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h
index e72a3db..f74e931 100644
--- a/bsp/sifive-hifive-unleashed/metal.h
+++ b/bsp/sifive-hifive-unleashed/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -141,7 +141,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller;
/* From interrupt_controller@c000000 */
struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
/* From gpio@10060000 */
struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000;
@@ -362,6 +362,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
}
}
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 8;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 8;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) {
+ return 8;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) {
+ return 8;
+ }
+ else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) {
+ return 8;
+ }
+ else {
+ return 0;
+ }
+}
+
/* --------------------- sifive_plic0 ------------ */
@@ -777,8 +799,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = {
#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
#define __MEE_DT_MAX_GPIOS 1
diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
index 3301bb0..f0f2a6d 100644
--- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
+++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
index cf43226..dd35e29 100644
--- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
+++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-11 */
+/* [XXXXX] 21-05-2019 10-54-35 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 05:20:09 +0000