diff options
Diffstat (limited to 'bsp/sifive-hifive-unleashed')
| -rw-r--r-- | bsp/sifive-hifive-unleashed/metal-platform.h | 119 | ||||
| -rw-r--r-- | bsp/sifive-hifive-unleashed/metal.h | 46 |
2 files changed, 143 insertions, 22 deletions
diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h new file mode 100644 index 0000000..db4360e --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal-platform.h @@ -0,0 +1,119 @@ +#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H +#define SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H + +/* From refclk */ +#define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL + +#define METAL_FIXED_CLOCK + +/* From tlclk */ +#define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL +#define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL + +#define METAL_FIXED_FACTOR_CLOCK + +/* From clint@2000000 */ +#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL +#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL + +#define METAL_RISCV_CLINT0 +#define METAL_RISCV_CLINT0_MSIP_BASE 0UL +#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL +#define METAL_RISCV_CLINT0_MTIME 49144UL + +/* From interrupt_controller@c000000 */ +#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL +#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL +#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL +#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 54UL + +#define METAL_RISCV_PLIC0 +#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL +#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL +#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL +#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL +#define METAL_RISCV_PLIC0_CLAIM 2097156UL + +/* From pmp@0 */ +#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL + +#define METAL_RISCV_PMP + +/* From gpio@10060000 */ +#define METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS 268828672UL +#define METAL_SIFIVE_GPIO0_10060000_SIZE 4096UL + +#define METAL_SIFIVE_GPIO0 +#define METAL_SIFIVE_GPIO0_VALUE 0UL +#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL +#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL +#define METAL_SIFIVE_GPIO0_PORT 12UL +#define METAL_SIFIVE_GPIO0_PUE 16UL +#define METAL_SIFIVE_GPIO0_DS 20UL +#define METAL_SIFIVE_GPIO0_RISE_IE 24UL +#define METAL_SIFIVE_GPIO0_RISE_IP 28UL +#define METAL_SIFIVE_GPIO0_FALL_IE 32UL +#define METAL_SIFIVE_GPIO0_FALL_IP 36UL +#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL +#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL +#define METAL_SIFIVE_GPIO0_LOW_IE 48UL +#define METAL_SIFIVE_GPIO0_LOW_IP 52UL +#define METAL_SIFIVE_GPIO0_IOF_EN 56UL +#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL +#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL + +/* From spi@10040000 */ +#define METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS 268697600UL +#define METAL_SIFIVE_SPI0_10040000_SIZE 4096UL + +/* From spi@10041000 */ +#define METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS 268701696UL +#define METAL_SIFIVE_SPI0_10041000_SIZE 4096UL + +/* From spi@10050000 */ +#define METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS 268763136UL +#define METAL_SIFIVE_SPI0_10050000_SIZE 4096UL + +#define METAL_SIFIVE_SPI0 +#define METAL_SIFIVE_SPI0_SCKDIV 0UL +#define METAL_SIFIVE_SPI0_SCKMODE 4UL +#define METAL_SIFIVE_SPI0_CSID 16UL +#define METAL_SIFIVE_SPI0_CSDEF 20UL +#define METAL_SIFIVE_SPI0_CSMODE 24UL +#define METAL_SIFIVE_SPI0_DELAY0 40UL +#define METAL_SIFIVE_SPI0_DELAY1 44UL +#define METAL_SIFIVE_SPI0_FMT 64UL +#define METAL_SIFIVE_SPI0_TXDATA 72UL +#define METAL_SIFIVE_SPI0_RXDATA 76UL +#define METAL_SIFIVE_SPI0_TXMARK 80UL +#define METAL_SIFIVE_SPI0_RXMARK 84UL +#define METAL_SIFIVE_SPI0_FCTRL 96UL +#define METAL_SIFIVE_SPI0_FFMT 100UL +#define METAL_SIFIVE_SPI0_IE 112UL +#define METAL_SIFIVE_SPI0_IP 116UL + +/* From teststatus@4000 */ +#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL +#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL + +#define METAL_SIFIVE_TEST0 +#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL + +/* From serial@10010000 */ +#define METAL_SIFIVE_UART0_10010000_BASE_ADDRESS 268500992UL +#define METAL_SIFIVE_UART0_10010000_SIZE 4096UL + +/* From serial@10011000 */ +#define METAL_SIFIVE_UART0_10011000_BASE_ADDRESS 268505088UL +#define METAL_SIFIVE_UART0_10011000_SIZE 4096UL + +#define METAL_SIFIVE_UART0 +#define METAL_SIFIVE_UART0_TXDATA 0UL +#define METAL_SIFIVE_UART0_RXDATA 4UL +#define METAL_SIFIVE_UART0_TXCTRL 8UL +#define METAL_SIFIVE_UART0_RXCTRL 12UL +#define METAL_SIFIVE_UART0_IE 16UL +#define METAL_SIFIVE_UART0_IP 20UL +#define METAL_SIFIVE_UART0_DIV 24UL + +#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H*/ diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h index b7a329b..118bdd3 100644 --- a/bsp/sifive-hifive-unleashed/metal.h +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -3,6 +3,8 @@ #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H #define SIFIVE_HIFIVE_UNLEASHED__METAL_H +#include <metal/machine/platform.h> + #ifdef __METAL_MACHINE_MACROS #define __METAL_CLINT_NUM_PARENTS 10 @@ -192,7 +194,7 @@ struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; struct __metal_driver_fixed_clock __metal_dt_refclk = { .vtable = &__metal_driver_vtable_fixed_clock, .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, - .rate = 33333333UL, + .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY, }; /* From tlclk */ @@ -201,8 +203,8 @@ struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = { .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock, /* From refclk */ .parent = &__metal_dt_refclk.clock, - .mult = 1, - .div = 2, + .mult = METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT, + .div = METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV, }; struct metal_memory __metal_dt_mem_dtim_1000000 = { @@ -317,8 +319,8 @@ struct metal_memory __metal_dt_mem_spi_10050000 = { struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, - .control_base = 33554432UL, - .control_size = 65536UL, + .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS, + .control_size = METAL_RISCV_CLINT0_2000000_SIZE, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, @@ -446,24 +448,24 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .interrupt_lines[7] = 11, .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, .interrupt_lines[8] = 9, - .control_base = 201326592UL, - .control_size = 67108864UL, - .max_priority = 7UL, - .num_interrupts = 54UL, + .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS, + .control_size = METAL_RISCV_PLIC0_C000000_SIZE, + .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY, + .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV, .interrupt_controller = 1, }; /* From pmp@0 */ struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = 1UL, + .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, }; /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { .vtable = &__metal_driver_vtable_sifive_gpio0, .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, - .base = 268828672UL, - .size = 4096UL, + .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS, + .size = METAL_SIFIVE_GPIO0_10060000_SIZE, /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, @@ -489,8 +491,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268697600UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10040000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -500,8 +502,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268701696UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10041000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -511,8 +513,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268763136UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10050000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -530,8 +532,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { .vtable = &__metal_driver_vtable_sifive_uart0, .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, - .control_base = 268500992UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_UART0_10010000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_UART0_10010000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -545,8 +547,8 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = { .vtable = &__metal_driver_vtable_sifive_uart0, .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, - .control_base = 268505088UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_UART0_10011000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_UART0_10011000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, |