diff options
Diffstat (limited to 'bsp/sifive-hifive1')
| -rw-r--r-- | bsp/sifive-hifive1/design.dts | 6 | ||||
| -rw-r--r-- | bsp/sifive-hifive1/mee.lds | 26 |
2 files changed, 26 insertions, 6 deletions
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index a71956a..26e4048 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -26,7 +26,6 @@ reg = <0>; riscv,isa = "rv32imac"; sifive,dtim = <&dtim>; - sifive,itim = <&itim>; status = "okay"; timebase-frequency = <1000000>; hlic: interrupt-controller { @@ -147,11 +146,6 @@ reg = <0x80000000 0x4000>; reg-names = "mem"; }; - itim: itim@8000000 { - compatible = "sifive,itim0"; - reg = <0x8000000 0x4000>; - reg-names = "mem"; - }; pwm@10015000 { compatible = "sifive,pwm0"; diff --git a/bsp/sifive-hifive1/mee.lds b/bsp/sifive-hifive1/mee.lds index cf24a7c..5a5a1aa 100644 --- a/bsp/sifive-hifive1/mee.lds +++ b/bsp/sifive-hifive1/mee.lds @@ -12,7 +12,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +119,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >ram AT>flash :ram_init + + + .itim : + { + *(.itim .itim.*) + } >flash AT>flash :flash + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); |