diff options
Diffstat (limited to 'bsp')
| -rw-r--r-- | bsp/coreip-e20-arty/settings.mk | 3 | ||||
| -rw-r--r-- | bsp/coreip-e20-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-e21-arty/settings.mk | 3 | ||||
| -rw-r--r-- | bsp/coreip-e21-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-e24-arty/settings.mk | 2 | ||||
| -rw-r--r-- | bsp/coreip-e24-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-e31-arty/settings.mk | 2 | ||||
| -rw-r--r-- | bsp/coreip-e31-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-e34-arty/settings.mk | 2 | ||||
| -rw-r--r-- | bsp/coreip-e34-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-e76-arty/settings.mk | 3 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-s51-arty/settings.mk | 2 | ||||
| -rw-r--r-- | bsp/coreip-s51-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-s54-arty/settings.mk | 4 | ||||
| -rw-r--r-- | bsp/coreip-s54-rtl/settings.mk | 5 | ||||
| -rw-r--r-- | bsp/coreip-s76-arty/settings.mk | 3 | ||||
| -rw-r--r-- | bsp/coreip-s76-rtl/settings.mk | 3 | ||||
| -rw-r--r-- | bsp/freedom-e310-arty/settings.mk | 6 | ||||
| -rw-r--r-- | bsp/sifive-hifive1-revb/settings.mk | 9 | ||||
| -rw-r--r-- | bsp/sifive-hifive1/settings.mk | 8 |
21 files changed, 65 insertions, 25 deletions
diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 31143b5..0b9c2cb 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,2 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 1ac4d9f..699498e 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index 31143b5..0b9c2cb 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,2 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index 32bb84d..f60f250 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index 32bb84d..f60f250 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index 32bb84d..f60f250 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index 32bb84d..f60f250 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 31143b5..0b9c2cb 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,2 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index fd049f4..dd09d48 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,6 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 3f994a3..2832d7c 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index a3cd0bb..4d48fc1 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,4 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -COREIP_MEM_WIDTH=64 RISCV_CMODEL=medany + +COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index ab3b474..2832d7c 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -iRISCV_CMODEL=medany +RISCV_CMODEL=medany + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index fabb838..4d48fc1 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,4 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -RISCV_CMODE=medany +RISCV_CMODEL=medany + COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index 1627f4b..2832d7c 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,2 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index a7d8dfa..4d48fc1 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,4 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany + COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index b7a7782..0b9c2cb 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,5 +1,5 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 -RISCV_CMODE=medlow +RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index 61e2b02..4c1f33e 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,4 +1,5 @@ -RISCV_ARCH = rv32imac -RISCV_ABI = ilp32 -RISCV_CMODEL = medlow -SEGGER_JLINK_OB = 1 +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +TARGET_TAGS=board jlink diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index fd73559..d863a6d 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,3 +1,5 @@ -RISCV_ARCH = rv32imac -RISCV_ABI = ilp32 -RISCV_CMODEL = medlow +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +TARGET_TAGS=board openocd |