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-rw-r--r--bsp/sifive-hifive1/design.dts6
1 files changed, 0 insertions, 6 deletions
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
index a71956a..26e4048 100644
--- a/bsp/sifive-hifive1/design.dts
+++ b/bsp/sifive-hifive1/design.dts
@@ -26,7 +26,6 @@
reg = <0>;
riscv,isa = "rv32imac";
sifive,dtim = <&dtim>;
- sifive,itim = <&itim>;
status = "okay";
timebase-frequency = <1000000>;
hlic: interrupt-controller {
@@ -147,11 +146,6 @@
reg = <0x80000000 0x4000>;
reg-names = "mem";
};
- itim: itim@8000000 {
- compatible = "sifive,itim0";
- reg = <0x8000000 0x4000>;
- reg-names = "mem";
- };
pwm@10015000 {
compatible = "sifive,pwm0";