diff options
Diffstat (limited to 'bsp')
26 files changed, 636 insertions, 78 deletions
diff --git a/bsp/drivers/fe300prci/fe300prci_driver.c b/bsp/drivers/fe300prci/fe300prci_driver.c index 2d9c52f..8eeaafc 100644 --- a/bsp/drivers/fe300prci/fe300prci_driver.c +++ b/bsp/drivers/fe300prci/fe300prci_driver.c @@ -2,7 +2,7 @@ #include "platform.h" -#ifdef PRCI_BASE_ADDR +#ifdef PRCI_CTRL_ADDR #include "fe300prci/fe300prci_driver.h" #include <unistd.h> diff --git a/bsp/env/common.mk b/bsp/env/common.mk index 74f5582..32703a6 100644 --- a/bsp/env/common.mk +++ b/bsp/env/common.mk @@ -8,7 +8,6 @@ all: $(TARGET) include $(BSP_BASE)/libwrap/libwrap.mk -BOARD ?= freedom-e300-hifive1 ENV_DIR = $(BSP_BASE)/env PLATFORM_DIR = $(ENV_DIR)/$(BOARD) @@ -25,9 +24,6 @@ INCLUDES += -I$(PLATFORM_DIR) TOOL_DIR = $(BSP_BASE)/../toolchain/bin -CC := $(TOOL_DIR)/riscv32-unknown-elf-gcc -AR := $(TOOL_DIR)/riscv32-unknown-elf-ar - LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles LDFLAGS += -L$(ENV_DIR) @@ -40,6 +36,9 @@ LINK_DEPS += $(LINKER_SCRIPT) CLEAN_OBJS += $(TARGET) $(LINK_OBJS) CFLAGS += -g +CFLAGS += -march=$(RISCV_ARCH) +CFLAGS += -mabi=$(RISCV_ABI) +CFLAGS += -mcmodel=medany $(TARGET): $(LINK_OBJS) $(LINK_DEPS) $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) diff --git a/bsp/env/coreplexip-arty.h b/bsp/env/coreplexip-arty.h new file mode 100644 index 0000000..12ff9a6 --- /dev/null +++ b/bsp/env/coreplexip-arty.h @@ -0,0 +1,102 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#define _SIFIVE_COREPLEXIP_ARTY_H + +#include <stdint.h> + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the directly driven +// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit. +// Additional RGB LEDs are driven by the 3 PWM outputs. + +#define RED_LED_OFFSET 0 +#define GREEN_LED_OFFSET 1 +#define BLUE_LED_OFFSET 2 + +// Switch 3 is used as a GPIO input. (Switch 0 is used to set +// the reset vector, the other switches are unused). + +#define SW_3_OFFSET 3 + +// These are the buttons which are mapped as inputs. + +#define HAS_BOARD_BUTTONS + +#define BUTTON_0_OFFSET 4 +#define BUTTON_1_OFFSET 5 +#define BUTTON_2_OFFSET 6 +#define BUTTON_3_OFFSET 7 + +// These are the bit offsets for the different GPIO pins +// mapped onto the PMOD A header. + +#define JA_0_OFFSET 8 +#define JA_1_OFFSET 9 +#define JA_2_OFFSET 10 +#define JA_3_OFFSET 11 +#define JA_4_OFFSET 12 +#define JA_5_OFFSET 13 +#define JA_6_OFFSET 14 +#define JA_7_OFFSET 15 + +// The below gives a mapping between global interrupt +// sources and their number. Note that on the coreplex +// deliverable, the io_global_interrupts go directly into +// the PLIC. The evaluation image on the FPGA mimics a +// system with peripheral devices which are driving the +// global interrupt lines. +// So, on this image, in order to get an interrupt from +// e.g. pressing BUTTON_0: +// 1) Steps which are external to the delivery coreplex: +// a) The corresponding GPIO pin must be configured as in input +// b) The "interrupt on fall" bit must be set for the GPIO pin +// 2) Steps which would also need to be performed for the delivery coreplex: +// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC. +// b) The external interrupt bit must be enabled in MSTATUS +// c) Interrupts must be enabled globally in the core. + +// Any of the above GPIO pins can be used as global interrupt +// sources by adding their offset to the INT_GPIO_BASE. +// For example, the buttons are shown here: + +#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET) +#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET) + +// In addition, the Switches are mapped directly to +// the PLIC (without going through the GPIO Peripheral). + +#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0) +#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1) +#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2) +#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3) + +// This gives the mapping from inputs to LOCAL interrupts. + +#define LOCAL_INT_SW_0 0 +#define LOCAL_INT_SW_1 1 +#define LOCAL_INT_SW_2 2 +#define LOCAL_INT_SW_3 3 +#define LOCAL_INT_BTN_0 4 +#define LOCAL_INT_BTN_1 5 +#define LOCAL_INT_BTN_2 6 +#define LOCAL_INT_BTN_3 7 +#define LOCAL_INT_JA_0 8 +#define LOCAL_INT_JA_1 9 +#define LOCAL_INT_JA_2 10 +#define LOCAL_INT_JA_3 11 +#define LOCAL_INT_JA_4 12 +#define LOCAL_INT_JA_5 13 +#define LOCAL_INT_JA_6 14 +#define LOCAL_INT_JA_7 15 + +#define RTC_FREQ 32768 + +void write_hex(int fd, uint32_t hex); + +#endif /* _SIFIVE_COREPLEXIP_ARTY_H */ diff --git a/bsp/env/coreplexip-e31-arty/init.c b/bsp/env/coreplexip-e31-arty/init.c new file mode 100644 index 0000000..05b2b3e --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/init.c @@ -0,0 +1,94 @@ +//See LICENSE for license details. +#include <stdint.h> +#include <stdio.h> +#include <unistd.h> + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +#ifdef USE_LOCAL_ISR +typedef void (*my_interrupt_function_ptr_t) (void); +extern my_interrupt_function_ptr_t localISR[]; +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif +#ifdef USE_LOCAL_ISR + } else if (mcause & MCAUSE_INT) { + localISR[mcause & MCAUSE_CAUSE] (); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/bsp/env/coreplexip-e31-arty/link.lds b/bsp/env/coreplexip-e31-arty/link.lds new file mode 100644 index 0000000..45a82d7 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/bsp/env/coreplexip-e31-arty/openocd.cfg b/bsp/env/coreplexip-e31-arty/openocd.cfg new file mode 100644 index 0000000..0481a72 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h new file mode 100644 index 0000000..02a0a62 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/platform.h @@ -0,0 +1,84 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#define IRQ_M_LOCAL 16 +#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x)) + +#include "sifive/const.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define GPIO_CTRL_ADDR _AC(0x20002000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define PWM0_CTRL_ADDR _AC(0x20005000,UL) +#define RAM_MEM_ADDR _AC(0x80000000,UL) +#define RAM_MEM_SIZE _AC(0x10000,UL) +#define SPI0_CTRL_ADDR _AC(0x20004000,UL) +#define SPI0_MEM_ADDR _AC(0x40000000,UL) +#define SPI0_MEM_SIZE _AC(0x20000000,UL) +#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL) +#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define UART0_CTRL_ADDR _AC(0x20000000,UL) + +// IOF masks + +// Interrupt numbers +#define RESERVED_INT_BASE 0 +#define UART0_INT_BASE 1 +#define EXTERNAL_INT_BASE 2 +#define SPI0_INT_BASE 6 +#define GPIO_INT_BASE 7 +#define PWM0_INT_BASE 23 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset) +#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset) + +// Misc + +#define NUM_GPIO 16 + +#define PLIC_NUM_INTERRUPTS 28 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS + +#include "coreplexip-arty.h" + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/bsp/env/coreplexip-e31-arty/settings.mk b/bsp/env/coreplexip-e31-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/coreplexip-e51-arty/init.c b/bsp/env/coreplexip-e51-arty/init.c new file mode 120000 index 0000000..de048a9 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/init.c @@ -0,0 +1 @@ +../coreplexip-e31-arty/init.c
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/link.lds b/bsp/env/coreplexip-e51-arty/link.lds new file mode 120000 index 0000000..f3e0254 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/link.lds @@ -0,0 +1 @@ +../coreplexip-e31-arty/link.lds
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/openocd.cfg b/bsp/env/coreplexip-e51-arty/openocd.cfg new file mode 120000 index 0000000..2f4de8d --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/openocd.cfg @@ -0,0 +1 @@ +../coreplexip-e31-arty/openocd.cfg
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/platform.h b/bsp/env/coreplexip-e51-arty/platform.h new file mode 120000 index 0000000..311ca36 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/platform.h @@ -0,0 +1 @@ +../coreplexip-e31-arty/platform.h
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/settings.mk b/bsp/env/coreplexip-e51-arty/settings.mk new file mode 100644 index 0000000..96aea84 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv64imac +RISCV_ABI := lp64 diff --git a/bsp/env/freedom-e300-arty/platform.h b/bsp/env/freedom-e300-arty/platform.h index d5d6dda..a3a3c07 100644 --- a/bsp/env/freedom-e300-arty/platform.h +++ b/bsp/env/freedom-e300-arty/platform.h @@ -20,21 +20,21 @@ * Platform definitions *****************************************************************************/ -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) #define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF Mappings #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -91,20 +91,20 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/bsp/env/freedom-e300-arty/settings.mk b/bsp/env/freedom-e300-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/freedom-e300-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c index de046cc..621a6e2 100644 --- a/bsp/env/freedom-e300-hifive1/init.c +++ b/bsp/env/freedom-e300-hifive1/init.c @@ -10,14 +10,14 @@ extern void trap_entry(); static unsigned long mtime_lo(void) { - return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); + return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME); } #ifdef __riscv32 static uint32_t mtime_hi(void) { - return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); } uint64_t get_timer_value() diff --git a/bsp/env/freedom-e300-hifive1/platform.h b/bsp/env/freedom-e300-hifive1/platform.h index 63efc9e..806fcfc 100644 --- a/bsp/env/freedom-e300-hifive1/platform.h +++ b/bsp/env/freedom-e300-hifive1/platform.h @@ -23,25 +23,25 @@ *****************************************************************************/ // Memory map -#define MASKROM_BASE_ADDR _AC(0x00001000,UL) -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define OTP_MMAP_ADDR _AC(0x00020000,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define PRCI_BASE_ADDR _AC(0x10008000,UL) -#define OTP_BASE_ADDR _AC(0x10010000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) -#define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MASKROM_MEM_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define OTP_MEM_ADDR _AC(0x00020000,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define PRCI_CTRL_ADDR _AC(0x10008000,UL) +#define OTP_CTRL_ADDR _AC(0x10010000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) +#define SPI0_MEM_ADDR _AC(0x20000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF masks #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -100,20 +100,20 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/bsp/env/freedom-e300-hifive1/settings.mk b/bsp/env/freedom-e300-hifive1/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/freedom-e300-hifive1/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/start.S b/bsp/env/start.S index b526411..9ec6c1c 100644 --- a/bsp/env/start.S +++ b/bsp/env/start.S @@ -1,5 +1,7 @@ // See LICENSE for license details. +// See LICENSE for license details. + .section .init .globl _start .type _start,@function @@ -50,5 +52,7 @@ _start: /* argc = argv = 0 */ li a0, 0 li a1, 0 + call _init call main + call _fini tail exit diff --git a/bsp/include/sifive/bits.h b/bsp/include/sifive/bits.h index e550f80..bfe656f 100644 --- a/bsp/include/sifive/bits.h +++ b/bsp/include/sifive/bits.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _RISCV_BITS_H #define _RISCV_BITS_H @@ -17,7 +18,7 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -#ifdef __riscv64 +#if __riscv_xlen == 64 # define SLL32 sllw # define STORE sd # define LOAD ld diff --git a/bsp/include/sifive/const.h b/bsp/include/sifive/const.h index 3e0a681..8dcffbb 100644 --- a/bsp/include/sifive/const.h +++ b/bsp/include/sifive/const.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. /* Derived from <linux/const.h> */ #ifndef _SIFIVE_CONST_H diff --git a/bsp/include/sifive/sections.h b/bsp/include/sifive/sections.h index 848c237..6e1f051 100644 --- a/bsp/include/sifive/sections.h +++ b/bsp/include/sifive/sections.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _SECTIONS_H #define _SECTIONS_H diff --git a/bsp/include/sifive/smp.h b/bsp/include/sifive/smp.h new file mode 100644 index 0000000..8e34388 --- /dev/null +++ b/bsp/include/sifive/smp.h @@ -0,0 +1,65 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + csrr reg2, mhartid ;\ + bnez reg2, 42f + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif diff --git a/bsp/libwrap/sys/_exit.c b/bsp/libwrap/sys/_exit.c index 7261891..a548a91 100644 --- a/bsp/libwrap/sys/_exit.c +++ b/bsp/libwrap/sys/_exit.c @@ -5,9 +5,7 @@ void __wrap__exit(int code) { -//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); const char message[] = "\nProgam has exited with code:"; -//*leds = (~(code)); write(STDERR_FILENO, message, sizeof(message) - 1); write_hex(STDERR_FILENO, code); diff --git a/bsp/libwrap/sys/read.c b/bsp/libwrap/sys/read.c index 4e57f08..4e35364 100644 --- a/bsp/libwrap/sys/read.c +++ b/bsp/libwrap/sys/read.c @@ -11,8 +11,8 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len) { uint8_t * current = (uint8_t *)ptr; - volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); - volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2); ssize_t result = 0; diff --git a/bsp/tools/openocd_upload.sh b/bsp/tools/openocd_upload.sh deleted file mode 100755 index ecbe3b4..0000000 --- a/bsp/tools/openocd_upload.sh +++ /dev/null @@ -1,5 +0,0 @@ -#! /bin/bash -x - -openocd -f ${2} \ - -c "flash protect 0 64 last off; program ${1} verify; resume 0x20400000; exit" \ - 2>&1 | tee openocd_upload.log |