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-rw-r--r--bsp/coreip-e31-arty/mee.lds27
-rw-r--r--bsp/coreip-e31/mee.lds27
-rw-r--r--bsp/coreip-s51-arty/mee.lds27
-rw-r--r--bsp/coreip-s51/mee.lds27
-rw-r--r--bsp/freedom-e310-arty/mee.lds27
-rw-r--r--bsp/sifive-hifive1/design.dts6
-rw-r--r--bsp/sifive-hifive1/mee.lds26
7 files changed, 161 insertions, 6 deletions
diff --git a/bsp/coreip-e31-arty/mee.lds b/bsp/coreip-e31-arty/mee.lds
index d0434f8..c081d9f 100644
--- a/bsp/coreip-e31-arty/mee.lds
+++ b/bsp/coreip-e31-arty/mee.lds
@@ -5,6 +5,7 @@ ENTRY(_enter)
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000
}
@@ -12,7 +13,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_NULL;
+ itim PT_NULL;
}
SECTIONS
@@ -117,6 +120,30 @@ SECTIONS
} >flash AT>flash :flash
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >flash AT>flash :flash
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>flash :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>flash :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
diff --git a/bsp/coreip-e31/mee.lds b/bsp/coreip-e31/mee.lds
index c446555..538291d 100644
--- a/bsp/coreip-e31/mee.lds
+++ b/bsp/coreip-e31/mee.lds
@@ -4,6 +4,7 @@ ENTRY(_enter)
MEMORY
{
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x8000000
}
@@ -11,7 +12,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_LOAD;
+ itim PT_LOAD;
}
SECTIONS
@@ -116,6 +119,30 @@ SECTIONS
} >ram AT>ram :ram
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >ram AT>ram :ram
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>ram :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>ram :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
diff --git a/bsp/coreip-s51-arty/mee.lds b/bsp/coreip-s51-arty/mee.lds
index d0434f8..c081d9f 100644
--- a/bsp/coreip-s51-arty/mee.lds
+++ b/bsp/coreip-s51-arty/mee.lds
@@ -5,6 +5,7 @@ ENTRY(_enter)
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000
}
@@ -12,7 +13,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_NULL;
+ itim PT_NULL;
}
SECTIONS
@@ -117,6 +120,30 @@ SECTIONS
} >flash AT>flash :flash
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >flash AT>flash :flash
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>flash :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>flash :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
diff --git a/bsp/coreip-s51/mee.lds b/bsp/coreip-s51/mee.lds
index 9f73234..3e454a7 100644
--- a/bsp/coreip-s51/mee.lds
+++ b/bsp/coreip-s51/mee.lds
@@ -4,6 +4,7 @@ ENTRY(_enter)
MEMORY
{
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x4000000
}
@@ -11,7 +12,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_LOAD;
+ itim PT_LOAD;
}
SECTIONS
@@ -116,6 +119,30 @@ SECTIONS
} >ram AT>ram :ram
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >ram AT>ram :ram
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>ram :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>ram :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
diff --git a/bsp/freedom-e310-arty/mee.lds b/bsp/freedom-e310-arty/mee.lds
index cf24a7c..8cd1a87 100644
--- a/bsp/freedom-e310-arty/mee.lds
+++ b/bsp/freedom-e310-arty/mee.lds
@@ -5,6 +5,7 @@ ENTRY(_enter)
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000
}
@@ -12,7 +13,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_NULL;
+ itim PT_NULL;
}
SECTIONS
@@ -117,6 +120,30 @@ SECTIONS
} >flash AT>flash :flash
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >flash AT>flash :flash
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>flash :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>flash :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
index a71956a..26e4048 100644
--- a/bsp/sifive-hifive1/design.dts
+++ b/bsp/sifive-hifive1/design.dts
@@ -26,7 +26,6 @@
reg = <0>;
riscv,isa = "rv32imac";
sifive,dtim = <&dtim>;
- sifive,itim = <&itim>;
status = "okay";
timebase-frequency = <1000000>;
hlic: interrupt-controller {
@@ -147,11 +146,6 @@
reg = <0x80000000 0x4000>;
reg-names = "mem";
};
- itim: itim@8000000 {
- compatible = "sifive,itim0";
- reg = <0x8000000 0x4000>;
- reg-names = "mem";
- };
pwm@10015000 {
compatible = "sifive,pwm0";
diff --git a/bsp/sifive-hifive1/mee.lds b/bsp/sifive-hifive1/mee.lds
index cf24a7c..5a5a1aa 100644
--- a/bsp/sifive-hifive1/mee.lds
+++ b/bsp/sifive-hifive1/mee.lds
@@ -12,7 +12,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_NULL;
+ itim PT_NULL;
}
SECTIONS
@@ -117,6 +119,30 @@ SECTIONS
} >flash AT>flash :flash
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >flash AT>flash :flash
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >ram AT>flash :ram_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >flash AT>flash :flash
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 17:48:13 +0000