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-rw-r--r--bsp/coreip-s51-arty/design.dts122
-rw-r--r--bsp/coreip-s51-arty/mee.h47
-rw-r--r--bsp/coreip-s51-arty/mee.lds190
-rw-r--r--bsp/coreip-s51-arty/settings.mk4
4 files changed, 363 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts
new file mode 100644
index 0000000..23362f2
--- /dev/null
+++ b/bsp/coreip-s51-arty/design.dts
@@ -0,0 +1,122 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "SiFive,FE510G-dev", "fe510-dev", "sifive-dev";
+ model = "SiFive,FE510G";
+
+ chosen {
+ stdout-path = "/soc/serial@20000000:115200";
+ mee,entry = <&L12 0x400000>;
+ };
+
+ L17: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ L6: cpu@0 {
+ clock-frequency = <0>;
+ compatible = "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&L12>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ sifive,dtim = <&L5>;
+ sifive,itim = <&L4>;
+ status = "okay";
+ timebase-frequency = <1000000>;
+ L3: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ L16: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus";
+ ranges;
+ L1: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&L3 3 &L3 7>;
+ reg = <0x2000000 0x10000>;
+ reg-names = "control";
+ };
+ L2: debug-controller@0 {
+ compatible = "sifive,debug-013", "riscv,debug-013";
+ interrupts-extended = <&L3 65535>;
+ reg = <0x0 0x1000>;
+ reg-names = "control";
+ };
+ L5: dtim@80000000 {
+ compatible = "sifive,dtim0";
+ reg = <0x80000000 0x10000>;
+ reg-names = "mem";
+ };
+ L8: error-device@3000 {
+ compatible = "sifive,error0";
+ reg = <0x3000 0x1000>;
+ reg-names = "mem";
+ };
+ L9: global-external-interrupts {
+ interrupt-parent = <&L0>;
+ interrupts = <1 2 3 4>;
+ };
+ L13: gpio@20002000 {
+ compatible = "sifive,gpio0";
+ interrupt-parent = <&L0>;
+ interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
+ reg = <0x20002000 0x1000>;
+ reg-names = "control";
+ };
+ L0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <&L3 11>;
+ reg = <0xc000000 0x4000000>;
+ reg-names = "control";
+ riscv,max-priority = <7>;
+ riscv,ndev = <26>;
+ };
+ L4: itim@8000000 {
+ compatible = "sifive,itim0";
+ reg = <0x8000000 0x4000>;
+ reg-names = "mem";
+ };
+ L10: local-external-interrupts-0 {
+ interrupt-parent = <&L3>;
+ interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
+ };
+ L14: pwm@20005000 {
+ compatible = "sifive,pwm0";
+ interrupt-parent = <&L0>;
+ interrupts = <23 24 25 26>;
+ reg = <0x20005000 0x1000>;
+ reg-names = "control";
+ };
+ L11: serial@20000000 {
+ compatible = "sifive,uart0";
+ interrupt-parent = <&L0>;
+ interrupts = <5>;
+ reg = <0x20000000 0x1000>;
+ reg-names = "control";
+ };
+ L12: spi@20004000 {
+ compatible = "sifive,spi0";
+ interrupt-parent = <&L0>;
+ interrupts = <6>;
+ reg = <0x20004000 0x1000 0x40000000 0x20000000>;
+ reg-names = "control", "mem";
+ };
+ L7: teststatus@4000 {
+ compatible = "sifive,test0";
+ reg = <0x4000 0x1000>;
+ reg-names = "control";
+ };
+ };
+};
diff --git a/bsp/coreip-s51-arty/mee.h b/bsp/coreip-s51-arty/mee.h
new file mode 100644
index 0000000..fe68d1f
--- /dev/null
+++ b/bsp/coreip-s51-arty/mee.h
@@ -0,0 +1,47 @@
+#ifndef ASSEMBLY
+#include <mee/drivers/sifive,gpio0.h>
+#include <mee/drivers/sifive,uart0.h>
+#include <mee/drivers/sifive,test0.h>
+/* From gpio@20002000 */
+asm (".weak __mee_dt_gpio_20002000");
+struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000;
+
+/* From serial@20000000 */
+asm (".weak __mee_dt_serial_20000000");
+struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000;
+
+/* From teststatus@4000 */
+asm (".weak __mee_dt_teststatus_4000");
+struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000;
+
+/* From gpio@20002000 */
+struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000 = {
+ .vtable = &__mee_driver_vtable_sifive_gpio0,
+ .base = 536879104UL,
+ .size = 4096UL,
+};
+
+/* From serial@20000000 */
+struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000 = {
+ .vtable = &__mee_driver_vtable_sifive_uart0,
+ .uart.vtable = &__mee_driver_vtable_sifive_uart0.uart,
+ .control_base = 536870912UL,
+ .control_size = 4096UL,
+ .clock = NULL,
+ .pinmux = NULL,
+};
+
+/* From teststatus@4000 */
+struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000 = {
+ .vtable = &__mee_driver_vtable_sifive_test0,
+ .shutdown.vtable = &__mee_driver_vtable_sifive_test0.shutdown,
+ .base = 16384UL,
+ .size = 4096UL,
+};
+
+/* From teststatus@4000 */
+#define __MEE_DT_SHUTDOWN_HANDLE (&__mee_dt_teststatus_4000.shutdown)
+/* From serial@20000000 */
+#define __MEE_DT_STDOUT_UART_HANDLE (&__mee_dt_serial_20000000.uart)
+#define __MEE_DT_STDOUT_UART_BAUD 115200
+#endif/*ASSEMBLY*/
diff --git a/bsp/coreip-s51-arty/mee.lds b/bsp/coreip-s51-arty/mee.lds
new file mode 100644
index 0000000..d0434f8
--- /dev/null
+++ b/bsp/coreip-s51-arty/mee.lds
@@ -0,0 +1,190 @@
+OUTPUT_ARCH("riscv")
+
+ENTRY(_enter)
+
+MEMORY
+{
+ ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000
+ flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000
+}
+
+PHDRS
+{
+ flash PT_LOAD;
+ ram_init PT_LOAD;
+ ram PT_NULL;
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 0x800;
+
+
+ .init :
+ {
+ KEEP (*(.text.mee.init.enter))
+ KEEP (*(SORT_NONE(.init)))
+ } >flash AT>flash :flash
+
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } >flash AT>flash :flash
+
+
+ .fini :
+ {
+ KEEP (*(SORT_NONE(.fini)))
+ } >flash AT>flash :flash
+
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.r.*)
+ } >flash AT>flash :flash
+
+
+ . = ALIGN(4);
+
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >flash AT>flash :flash
+
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >flash AT>flash :flash
+
+
+ .finit_array :
+ {
+ PROVIDE_HIDDEN (__finit_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__finit_array_end = .);
+ } >flash AT>flash :flash
+
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >flash AT>flash :flash
+
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >flash AT>flash :flash
+
+
+ .lalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( _data_lma = . );
+ PROVIDE( mee_segment_data_source_start = . );
+ } >flash AT>flash :flash
+
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_data_target_start = . );
+ } >ram AT>flash :ram_init
+
+
+ .data :
+ {
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ } >ram AT>flash :ram_init
+
+
+ . = ALIGN(4);
+ PROVIDE( _edata = . );
+ PROVIDE( edata = . );
+ PROVIDE( mee_segment_data_target_end = . );
+ PROVIDE( _fbss = . );
+ PROVIDE( __bss_start = . );
+ PROVIDE( mee_segment_bss_target_start = . );
+
+
+ .bss :
+ {
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ } >ram AT>ram :ram
+
+
+ . = ALIGN(8);
+ PROVIDE( _end = . );
+ PROVIDE( end = . );
+ PROVIDE( mee_segment_bss_target_end = . );
+ PROVIDE( mee_segment_heap_target_start = . );
+
+
+ .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+ {
+ PROVIDE( mee_segment_heap_target_end = . );
+ PROVIDE( _heap_end = . );
+ . = __stack_size;
+ PROVIDE( _sp = . );
+ PROVIDE(mee_segment_stack_end = .);
+ } >ram AT>ram :ram
+
+
+}
+
diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk
new file mode 100644
index 0000000..31aca11
--- /dev/null
+++ b/bsp/coreip-s51-arty/settings.mk
@@ -0,0 +1,4 @@
+#write_config_file
+
+RISCV_ARCH=rv64imac
+RISCV_ABI=lp64
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 18:08:18 +0000