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-rw-r--r--bsp/coreip-e24-arty/design.dts1
-rw-r--r--bsp/coreip-e31-arty/design.dts1
-rw-r--r--bsp/coreip-e31/design.dts1
-rw-r--r--bsp/coreip-s51-arty/design.dts1
-rw-r--r--bsp/coreip-s51/design.dts1
-rw-r--r--bsp/freedom-e310-arty/design.dts1
-rw-r--r--bsp/sifive-hifive1/design.dts1
-rwxr-xr-xbsp/update-targets.sh2
8 files changed, 7 insertions, 2 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts
index 780cc7b..9699fae 100644
--- a/bsp/coreip-e24-arty/design.dts
+++ b/bsp/coreip-e24-arty/design.dts
@@ -23,6 +23,7 @@
riscv,isa = "rv32imafc";
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts
index c69740e..03e100b 100644
--- a/bsp/coreip-e31-arty/design.dts
+++ b/bsp/coreip-e31-arty/design.dts
@@ -28,6 +28,7 @@
sifive,itim = <&L4>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts
index f7e9868..c589362 100644
--- a/bsp/coreip-e31/design.dts
+++ b/bsp/coreip-e31/design.dts
@@ -21,6 +21,7 @@
sifive,itim = <&L4>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts
index 6c7379d..0378ec3 100644
--- a/bsp/coreip-s51-arty/design.dts
+++ b/bsp/coreip-s51-arty/design.dts
@@ -28,6 +28,7 @@
sifive,itim = <&L4>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/coreip-s51/design.dts b/bsp/coreip-s51/design.dts
index a1cb9fc..9cf3a29 100644
--- a/bsp/coreip-s51/design.dts
+++ b/bsp/coreip-s51/design.dts
@@ -21,6 +21,7 @@
sifive,itim = <&L4>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/freedom-e310-arty/design.dts b/bsp/freedom-e310-arty/design.dts
index 74da572..0935af9 100644
--- a/bsp/freedom-e310-arty/design.dts
+++ b/bsp/freedom-e310-arty/design.dts
@@ -29,6 +29,7 @@
sifive,itim = <&itim>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
hlic: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
index abccd6c..ff95ae0 100644
--- a/bsp/sifive-hifive1/design.dts
+++ b/bsp/sifive-hifive1/design.dts
@@ -28,6 +28,7 @@
sifive,dtim = <&dtim>;
status = "okay";
timebase-frequency = <1000000>;
+ hardware-exec-breakpoint-count = <4>;
hlic: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
diff --git a/bsp/update-targets.sh b/bsp/update-targets.sh
index 049cbb1..8f094e5 100755
--- a/bsp/update-targets.sh
+++ b/bsp/update-targets.sh
@@ -7,7 +7,6 @@ $0: BSP Generator for the SiFive Freedom E SDK
--target-name Specify bsp target name.
--sdk-path=* The path to the freedom-e-sdk clone directory, public or private.
--target-dts=*.dts The path to the target device tree that will be used.
- --ipdelivery-tgz=*.tar.gz The path to the ipdelivery that will be used.
EOF
}
@@ -82,7 +81,6 @@ update_target() {
echo ""
}
-echo $PWD
for TARGET in $TARGET_LIST
do
update_target $TARGET