diff options
Diffstat (limited to 'bsp')
38 files changed, 3028 insertions, 154 deletions
diff --git a/bsp/coreip-e20/settings.mk b/bsp/coreip-e20/settings.mk index 50c6504..1ac4d9f 100644 --- a/bsp/coreip-e20/settings.mk +++ b/bsp/coreip-e20/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imc RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e21/settings.mk b/bsp/coreip-e21/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e21/settings.mk +++ b/bsp/coreip-e21/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e24-arty/README.md b/bsp/coreip-e24-arty/README.md new file mode 100644 index 0000000..79dfae8 --- /dev/null +++ b/bsp/coreip-e24-arty/README.md @@ -0,0 +1,13 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 31143b5..829d3e8 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow diff --git a/bsp/coreip-e24/settings.mk b/bsp/coreip-e24/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e24/settings.mk +++ b/bsp/coreip-e24/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index 03e100b..2500df0 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -5,31 +5,32 @@ #size-cells = <1>; compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev"; model = "SiFive,FE310G"; - chosen { stdout-path = "/soc/serial@20000000:115200"; - metal,entry = <&L12 0x400000>; + metal,entry = <&L10 0x400000>; }; - + L18: aliases { + serial0 = &L9; + }; L17: cpus { #address-cells = <1>; #size-cells = <0>; - L6: cpu@0 { + L7: cpu@0 { clock-frequency = <0>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <128>; i-cache-size = <16384>; - next-level-cache = <&L12>; - reg = <0>; + next-level-cache = <&L10>; + reg = <0x0>; riscv,isa = "rv32imac"; - sifive,dtim = <&L5>; - sifive,itim = <&L4>; + sifive,dtim = <&L6>; + sifive,itim = <&L5>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; - L3: interrupt-controller { + L4: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; @@ -50,153 +51,158 @@ compatible = "riscv,pmp"; regions = <8>; }; - L1: clint@2000000 { + L2: clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&L3 3 &L3 7>; + interrupts-extended = <&L4 3 &L4 7>; reg = <0x2000000 0x10000>; reg-names = "control"; }; - L2: debug-controller@0 { + L3: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L3 65535>; + interrupts-extended = <&L4 65535>; reg = <0x0 0x1000>; reg-names = "control"; }; - L5: dtim@80000000 { + L6: dtim@80000000 { compatible = "sifive,dtim0"; reg = <0x80000000 0x10000>; reg-names = "mem"; }; - L8: error-device@3000 { + L0: error-device@3000 { compatible = "sifive,error0"; reg = <0x3000 0x1000>; - reg-names = "mem"; - }; - L9: global-external-interrupts { + }; + L13: global-external-interrupts { compatible = "sifive,global-external-interrupts0"; - interrupt-parent = <&L0>; - interrupts = <1 2 3 4>; + interrupt-parent = <&L1>; + interrupts = <23 24 25 26>; }; - L13: gpio@20002000 { - compatible = "sifive,gpio0"; - interrupt-parent = <&L0>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + L8: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0", "sifive,gpio1"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; reg = <0x20002000 0x1000>; reg-names = "control"; }; - L0: interrupt-controller@c000000 { + L1: interrupt-controller@c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; interrupt-controller; - interrupts-extended = <&L3 11>; + interrupts-extended = <&L4 11>; reg = <0xc000000 0x4000000>; reg-names = "control"; riscv,max-priority = <7>; riscv,ndev = <26>; }; - L4: itim@8000000 { + L5: itim@8000000 { compatible = "sifive,itim0"; reg = <0x8000000 0x4000>; reg-names = "mem"; }; - L10: local-external-interrupts-0 { + L14: local-external-interrupts-0 { compatible = "sifive,local-external-interrupts0"; - interrupt-parent = <&L3>; + interrupt-parent = <&L4>; interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; - L14: pwm@20005000 { + L11: pwm@20005000 { compatible = "sifive,pwm0"; - interrupt-parent = <&L0>; - interrupts = <23 24 25 26>; + interrupt-parent = <&L1>; + interrupts = <19 20 21 22>; reg = <0x20005000 0x1000>; reg-names = "control"; }; - L11: serial@20000000 { + L9: serial@20000000 { compatible = "sifive,uart0"; - interrupt-parent = <&L0>; - interrupts = <5>; + interrupt-parent = <&L1>; + interrupts = <17>; reg = <0x20000000 0x1000>; reg-names = "control"; clocks = <&hfclk>; }; - L12: spi@20004000 { + L10: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "sifive,spi0"; - interrupt-parent = <&L0>; - interrupts = <6>; + interrupt-parent = <&L1>; + interrupts = <18>; reg = <0x20004000 0x1000 0x40000000 0x20000000>; reg-names = "control", "mem"; }; led@0red { compatible = "sifive,gpio-leds"; label = "LD0red"; - gpios = <&L13 0>; + gpios = <&L8 0>; linux,default-trigger = "none"; }; led@0green { compatible = "sifive,gpio-leds"; label = "LD0green"; - gpios = <&L13 1>; + gpios = <&L8 1>; linux,default-trigger = "none"; }; led@0blue { compatible = "sifive,gpio-leds"; label = "LD0blue"; - gpios = <&L13 2>; + gpios = <&L8 2>; linux,default-trigger = "none"; }; button@0 { compatible = "sifive,gpio-buttons"; label = "BTN0"; - gpios = <&L13 4>; - interrupts-extended = <&L10 4>; + gpios = <&L8 4>; + interrupts-extended = <&L14 4>; linux,code = "none"; }; button@1 { compatible = "sifive,gpio-buttons"; label = "BTN1"; - gpios = <&L13 5>; - interrupts-extended = <&L10 5>; + gpios = <&L8 5>; + interrupts-extended = <&L14 5>; linux,code = "none"; }; button@2 { compatible = "sifive,gpio-buttons"; label = "BTN2"; - gpios = <&L13 6>; - interrupts-extended = <&L10 6>; + gpios = <&L8 6>; + interrupts-extended = <&L14 6>; linux,code = "none"; }; button@3 { compatible = "sifive,gpio-buttons"; label = "BTN3"; - gpios = <&L13 7>; - interrupts-extended = <&L10 7>; + gpios = <&L8 7>; + interrupts-extended = <&L14 7>; linux,code = "none"; }; switch@0 { compatible = "sifive,gpio-switches"; label = "SW0"; - interrupts-extended = <&L9 0>; + interrupts-extended = <&L13 0>; linux,code = "none"; }; switch@1 { compatible = "sifive,gpio-switches"; label = "SW1"; - interrupts-extended = <&L9 1>; + interrupts-extended = <&L13 1>; linux,code = "none"; }; switch@2 { compatible = "sifive,gpio-switches"; label = "SW2"; - interrupts-extended = <&L9 2>; + interrupts-extended = <&L13 2>; linux,code = "none"; }; switch@3 { compatible = "sifive,gpio-switches"; label = "SW3"; - interrupts-extended = <&L10 3>; + interrupts-extended = <&L14 3>; linux,code = "none"; }; - L7: teststatus@4000 { + L12: teststatus@4000 { compatible = "sifive,test0"; reg = <0x4000 0x1000>; reg-names = "control"; diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h index 8c2ead9..62dac06 100644 --- a/bsp/coreip-e31-arty/metal.h +++ b/bsp/coreip-e31-arty/metal.h @@ -235,10 +235,10 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, - .interrupt_lines[0] = 1, - .interrupt_lines[1] = 2, - .interrupt_lines[2] = 3, - .interrupt_lines[3] = 4, + .interrupt_lines[0] = 23, + .interrupt_lines[1] = 24, + .interrupt_lines[2] = 25, + .interrupt_lines[3] = 26, }; /* From gpio@20002000 */ @@ -249,22 +249,22 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = { /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, - .interrupt_lines[0] = 7, - .interrupt_lines[1] = 8, - .interrupt_lines[2] = 9, - .interrupt_lines[3] = 10, - .interrupt_lines[4] = 11, - .interrupt_lines[5] = 12, - .interrupt_lines[6] = 13, - .interrupt_lines[7] = 14, - .interrupt_lines[8] = 15, - .interrupt_lines[9] = 16, - .interrupt_lines[10] = 17, - .interrupt_lines[11] = 18, - .interrupt_lines[12] = 19, - .interrupt_lines[13] = 20, - .interrupt_lines[14] = 21, - .interrupt_lines[15] = 22, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, }; /* From button@0 */ @@ -427,7 +427,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_UART_INTERRUPTS, - .interrupt_line = 5UL, + .interrupt_line = 17UL, }; diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index 31143b5..829d3e8 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow diff --git a/bsp/coreip-e31/settings.mk b/bsp/coreip-e31/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e31/settings.mk +++ b/bsp/coreip-e31/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e34-arty/README.md b/bsp/coreip-e34-arty/README.md new file mode 100644 index 0000000..ce867af --- /dev/null +++ b/bsp/coreip-e34-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E34 Standard Core adds single-precision floating-point to the SiFive E31 Standard Core, the world’s most deployed RISC-V core. The E34 enables advanced applications which require hardware floating-point capabilities such as signal processing and motor control. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-e34-arty/design.dts b/bsp/coreip-e34-arty/design.dts new file mode 100644 index 0000000..55f3d23 --- /dev/null +++ b/bsp/coreip-e34-arty/design.dts @@ -0,0 +1,211 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev"; + model = "SiFive,FE310G"; + chosen { + stdout-path = "/soc/serial@20000000:115200"; + metal,entry = <&L10 0x400000>; + }; + L18: aliases { + serial0 = &L9; + }; + L17: cpus { + #address-cells = <1>; + #size-cells = <0>; + L7: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L10>; + reg = <0x0>; + riscv,isa = "rv32imafc"; + sifive,dtim = <&L6>; + sifive,itim = <&L5>; + status = "okay"; + timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; + L4: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus"; + ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + L2: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L4 3 &L4 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L3: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L4 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L6: dtim@80000000 { + compatible = "sifive,dtim0"; + reg = <0x80000000 0x10000>; + reg-names = "mem"; + }; + L0: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L13: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; + interrupt-parent = <&L1>; + interrupts = <23 24 25 26>; + }; + L8: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0", "sifive,gpio1"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; + reg = <0x20002000 0x1000>; + reg-names = "control"; + }; + L1: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L4 11>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <26>; + }; + L5: itim@8000000 { + compatible = "sifive,itim0"; + reg = <0x8000000 0x4000>; + reg-names = "mem"; + }; + L14: local-external-interrupts-0 { + compatible = "sifive,local-external-interrupts0"; + interrupt-parent = <&L4>; + interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; + L11: pwm@20005000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L1>; + interrupts = <19 20 21 22>; + reg = <0x20005000 0x1000>; + reg-names = "control"; + }; + L9: serial@20000000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L1>; + interrupts = <17>; + reg = <0x20000000 0x1000>; + reg-names = "control"; + clocks = <&hfclk>; + }; + L10: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sifive,spi0"; + interrupt-parent = <&L1>; + interrupts = <18>; + reg = <0x20004000 0x1000 0x40000000 0x20000000>; + reg-names = "control", "mem"; + }; + led@0red { + compatible = "sifive,gpio-leds"; + label = "LD0red"; + gpios = <&L8 0>; + linux,default-trigger = "none"; + }; + led@0green { + compatible = "sifive,gpio-leds"; + label = "LD0green"; + gpios = <&L8 1>; + linux,default-trigger = "none"; + }; + led@0blue { + compatible = "sifive,gpio-leds"; + label = "LD0blue"; + gpios = <&L8 2>; + linux,default-trigger = "none"; + }; + button@0 { + compatible = "sifive,gpio-buttons"; + label = "BTN0"; + gpios = <&L8 4>; + interrupts-extended = <&L14 4>; + linux,code = "none"; + }; + button@1 { + compatible = "sifive,gpio-buttons"; + label = "BTN1"; + gpios = <&L8 5>; + interrupts-extended = <&L14 5>; + linux,code = "none"; + }; + button@2 { + compatible = "sifive,gpio-buttons"; + label = "BTN2"; + gpios = <&L8 6>; + interrupts-extended = <&L14 6>; + linux,code = "none"; + }; + button@3 { + compatible = "sifive,gpio-buttons"; + label = "BTN3"; + gpios = <&L8 7>; + interrupts-extended = <&L14 7>; + linux,code = "none"; + }; + switch@0 { + compatible = "sifive,gpio-switches"; + label = "SW0"; + interrupts-extended = <&L13 0>; + linux,code = "none"; + }; + switch@1 { + compatible = "sifive,gpio-switches"; + label = "SW1"; + interrupts-extended = <&L13 1>; + linux,code = "none"; + }; + switch@2 { + compatible = "sifive,gpio-switches"; + label = "SW2"; + interrupts-extended = <&L13 2>; + linux,code = "none"; + }; + switch@3 { + compatible = "sifive,gpio-switches"; + label = "SW3"; + interrupts-extended = <&L14 3>; + linux,code = "none"; + }; + L12: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h new file mode 100644 index 0000000..768fd66 --- /dev/null +++ b/bsp/coreip-e34-arty/metal.h @@ -0,0 +1,520 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_E34_ARTY__METAL_H +#define COREIP_E34_ARTY__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 2 + +#define METAL_MAX_CLINT_INTERRUPTS 2 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 + +#define METAL_MAX_PLIC_INTERRUPTS 1 + +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define __METAL_LOCAL_EXTERNAL_INTERRUPTS_0_INTERRUPTS 16 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 16 + +#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 4 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 4 + +#define __METAL_GPIO_20002000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_20000000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,local-external-interrupts0.h> +#include <metal/drivers/sifive,global-external-interrupts0.h> +#include <metal/drivers/sifive,gpio0.h> +#include <metal/drivers/sifive,gpio-buttons.h> +#include <metal/drivers/sifive,gpio-leds.h> +#include <metal/drivers/sifive,gpio-switches.h> +#include <metal/drivers/sifive,spi0.h> +#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive,uart0.h> + +/* From clock@0 */ +asm (".weak __metal_dt_clock_0"); +struct __metal_driver_fixed_clock __metal_dt_clock_0; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __metal_dt_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From local_external_interrupts_0 */ +asm (".weak __metal_dt_local_external_interrupts_0"); +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; + +/* From global_external_interrupts */ +asm (".weak __metal_dt_global_external_interrupts"); +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; + +/* From gpio@20002000 */ +asm (".weak __metal_dt_gpio_20002000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000; + +/* From button@0 */ +asm (".weak __metal_dt_button_0"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_0; + +/* From button@1 */ +asm (".weak __metal_dt_button_1"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_1; + +/* From button@2 */ +asm (".weak __metal_dt_button_2"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_2; + +/* From button@3 */ +asm (".weak __metal_dt_button_3"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_3; + +/* From led@0red */ +asm (".weak __metal_dt_led_0red"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red; + +/* From led@0green */ +asm (".weak __metal_dt_led_0green"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green; + +/* From led@0blue */ +asm (".weak __metal_dt_led_0blue"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue; + +/* From switch@0 */ +asm (".weak __metal_dt_switch_0"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0; + +/* From switch@1 */ +asm (".weak __metal_dt_switch_1"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1; + +/* From switch@2 */ +asm (".weak __metal_dt_switch_2"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2; + +/* From switch@3 */ +asm (".weak __metal_dt_switch_3"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3; + +/* From spi@20004000 */ +asm (".weak __metal_dt_spi_20004000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From serial@20000000 */ +asm (".weak __metal_dt_serial_20000000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000; + + +/* From clock@0 */ +struct __metal_driver_fixed_clock __metal_dt_clock_0 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 32500000UL, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_lines[1] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_line = 11UL, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 26UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From local_external_interrupts_0 */ +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { + .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 16, + .interrupt_lines[1] = 17, + .interrupt_lines[2] = 18, + .interrupt_lines[3] = 19, + .interrupt_lines[4] = 20, + .interrupt_lines[5] = 21, + .interrupt_lines[6] = 22, + .interrupt_lines[7] = 23, + .interrupt_lines[8] = 24, + .interrupt_lines[9] = 25, + .interrupt_lines[10] = 26, + .interrupt_lines[11] = 27, + .interrupt_lines[12] = 28, + .interrupt_lines[13] = 29, + .interrupt_lines[14] = 30, + .interrupt_lines[15] = 31, +}; + +/* From global_external_interrupts */ +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { + .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, + .init_done = 0, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 23, + .interrupt_lines[1] = 24, + .interrupt_lines[2] = 25, + .interrupt_lines[3] = 26, +}; + +/* From gpio@20002000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .base = 536879104UL, + .size = 4096UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, +}; + +/* From button@0 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 4UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 4UL, + .label = "BTN0", +}; + +/* From button@1 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 5UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 5UL, + .label = "BTN1", +}; + +/* From button@2 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 6UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 6UL, + .label = "BTN2", +}; + +/* From button@3 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 7UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 7UL, + .label = "BTN3", +}; + +/* From led@0red */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 0UL, + .label = "LD0red", +}; + +/* From led@0green */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 1UL, + .label = "LD0green", +}; + +/* From led@0blue */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 2UL, + .label = "LD0blue", +}; + +/* From switch@0 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 0UL, + .label = "SW0", +}; + +/* From switch@1 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 1UL, + .label = "SW1", +}; + +/* From switch@2 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 2UL, + .label = "SW2", +}; + +/* From switch@3 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 3UL, + .label = "SW3", +}; + +/* From spi@20004000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 536887296UL, + .control_size = 4096UL, + .clock = NULL, + .pinmux = NULL, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From serial@20000000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 536870912UL, + .control_size = 4096UL, +/* From clock@0 */ + .clock = &__metal_dt_clock_0.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 17UL, +}; + + +/* From serial@20000000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_SERIAL_20000000_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +/* From cpu@0 */ +#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller */ +#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From local_external_interrupts_0 */ +#define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_LOCAL_EXTERNAL_INTERRUPTS_0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +/* From global_external_interrupts */ +#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_MAX_BUTTONS 4 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + &__metal_dt_button_0, + &__metal_dt_button_1, + &__metal_dt_button_2, + &__metal_dt_button_3}; + +#define __METAL_DT_MAX_LEDS 3 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + &__metal_dt_led_0red, + &__metal_dt_led_0green, + &__metal_dt_led_0blue}; + +#define __METAL_DT_MAX_SWITCHES 4 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + &__metal_dt_switch_0, + &__metal_dt_switch_1, + &__metal_dt_switch_2, + &__metal_dt_switch_3}; + +#define __METAL_DT_MAX_SPIS 1 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_20004000}; + +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_E34_ARTY__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-e34-arty/metal.lds b/bsp/coreip-e34-arty/metal.lds new file mode 100644 index 0000000..28a7849 --- /dev/null +++ b/bsp/coreip-e34-arty/metal.lds @@ -0,0 +1,226 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-e34-arty/openocd.cfg b/bsp/coreip-e34-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e34-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk new file mode 100644 index 0000000..829d3e8 --- /dev/null +++ b/bsp/coreip-e34-arty/settings.mk @@ -0,0 +1,3 @@ +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +RISCV_CMODEL=medlow diff --git a/bsp/coreip-e34/settings.mk b/bsp/coreip-e34/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e34/settings.mk +++ b/bsp/coreip-e34/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e76/settings.mk b/bsp/coreip-e76/settings.mk index 3dcc8c7..fd049f4 100644 --- a/bsp/coreip-e76/settings.mk +++ b/bsp/coreip-e76/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=64 diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 0378ec3..137e7d8 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -3,33 +3,34 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "SiFive,FE510G-dev", "fe510-dev", "sifive-dev"; - model = "SiFive,FE510G"; - + compatible = "SiFive,FS510G-dev", "fs510-dev", "sifive-dev"; + model = "SiFive,FS510G"; chosen { stdout-path = "/soc/serial@20000000:115200"; - metal,entry = <&L12 0x400000>; + metal,entry = <&L10 0x400000>; }; - + L18: aliases { + serial0 = &L9; + }; L17: cpus { #address-cells = <1>; #size-cells = <0>; - L6: cpu@0 { + L7: cpu@0 { clock-frequency = <0>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <128>; i-cache-size = <16384>; - next-level-cache = <&L12>; - reg = <0>; + next-level-cache = <&L10>; + reg = <0x0>; riscv,isa = "rv64imac"; - sifive,dtim = <&L5>; - sifive,itim = <&L4>; + sifive,dtim = <&L6>; + sifive,itim = <&L5>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; - L3: interrupt-controller { + L4: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; @@ -39,7 +40,7 @@ L16: soc { #address-cells = <1>; #size-cells = <1>; - compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus"; + compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus"; ranges; hfclk: clock@0 { #clock-cells = <0>; @@ -50,153 +51,158 @@ compatible = "riscv,pmp"; regions = <8>; }; - L1: clint@2000000 { + L2: clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&L3 3 &L3 7>; + interrupts-extended = <&L4 3 &L4 7>; reg = <0x2000000 0x10000>; reg-names = "control"; }; - L2: debug-controller@0 { + L3: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L3 65535>; + interrupts-extended = <&L4 65535>; reg = <0x0 0x1000>; reg-names = "control"; }; - L5: dtim@80000000 { + L6: dtim@80000000 { compatible = "sifive,dtim0"; reg = <0x80000000 0x10000>; reg-names = "mem"; }; - L8: error-device@3000 { + L0: error-device@3000 { compatible = "sifive,error0"; reg = <0x3000 0x1000>; - reg-names = "mem"; }; - L9: global-external-interrupts { + L13: global-external-interrupts { compatible = "sifive,global-external-interrupts0"; - interrupt-parent = <&L0>; - interrupts = <1 2 3 4>; + interrupt-parent = <&L1>; + interrupts = <23 24 25 26>; }; - L13: gpio@20002000 { - compatible = "sifive,gpio0"; - interrupt-parent = <&L0>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + L8: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0", "sifive,gpio1"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; reg = <0x20002000 0x1000>; reg-names = "control"; }; - L0: interrupt-controller@c000000 { + L1: interrupt-controller@c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; interrupt-controller; - interrupts-extended = <&L3 11>; + interrupts-extended = <&L4 11>; reg = <0xc000000 0x4000000>; reg-names = "control"; riscv,max-priority = <7>; riscv,ndev = <26>; }; - L4: itim@8000000 { + L5: itim@8000000 { compatible = "sifive,itim0"; reg = <0x8000000 0x4000>; reg-names = "mem"; }; - L10: local-external-interrupts-0 { + L14: local-external-interrupts-0 { compatible = "sifive,local-external-interrupts0"; - interrupt-parent = <&L3>; + interrupt-parent = <&L4>; interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; - L14: pwm@20005000 { + L11: pwm@20005000 { compatible = "sifive,pwm0"; - interrupt-parent = <&L0>; - interrupts = <23 24 25 26>; + interrupt-parent = <&L1>; + interrupts = <19 20 21 22>; reg = <0x20005000 0x1000>; reg-names = "control"; }; - L11: serial@20000000 { + L9: serial@20000000 { compatible = "sifive,uart0"; - interrupt-parent = <&L0>; - interrupts = <5>; + interrupt-parent = <&L1>; + interrupts = <17>; reg = <0x20000000 0x1000>; reg-names = "control"; clocks = <&hfclk>; }; - L12: spi@20004000 { + L10: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "sifive,spi0"; - interrupt-parent = <&L0>; - interrupts = <6>; + interrupt-parent = <&L1>; + interrupts = <18>; reg = <0x20004000 0x1000 0x40000000 0x20000000>; reg-names = "control", "mem"; }; led@0red { compatible = "sifive,gpio-leds"; label = "LD0red"; - gpios = <&L13 0>; + gpios = <&L8 0>; linux,default-trigger = "none"; }; led@0green { compatible = "sifive,gpio-leds"; label = "LD0green"; - gpios = <&L13 1>; + gpios = <&L8 1>; linux,default-trigger = "none"; }; led@0blue { compatible = "sifive,gpio-leds"; label = "LD0blue"; - gpios = <&L13 2>; + gpios = <&L8 2>; linux,default-trigger = "none"; }; button@0 { compatible = "sifive,gpio-buttons"; label = "BTN0"; - gpios = <&L13 4>; - interrupts-extended = <&L10 4>; + gpios = <&L8 4>; + interrupts-extended = <&L14 4>; linux,code = "none"; }; button@1 { compatible = "sifive,gpio-buttons"; label = "BTN1"; - gpios = <&L13 5>; - interrupts-extended = <&L10 5>; + gpios = <&L8 5>; + interrupts-extended = <&L14 5>; linux,code = "none"; }; button@2 { compatible = "sifive,gpio-buttons"; label = "BTN2"; - gpios = <&L13 6>; - interrupts-extended = <&L10 6>; + gpios = <&L8 6>; + interrupts-extended = <&L14 6>; linux,code = "none"; }; button@3 { compatible = "sifive,gpio-buttons"; label = "BTN3"; - gpios = <&L13 7>; - interrupts-extended = <&L10 7>; + gpios = <&L8 7>; + interrupts-extended = <&L14 7>; linux,code = "none"; }; switch@0 { compatible = "sifive,gpio-switches"; label = "SW0"; - interrupts-extended = <&L9 0>; + interrupts-extended = <&L13 0>; linux,code = "none"; }; switch@1 { compatible = "sifive,gpio-switches"; label = "SW1"; - interrupts-extended = <&L9 1>; + interrupts-extended = <&L13 1>; linux,code = "none"; }; switch@2 { compatible = "sifive,gpio-switches"; label = "SW2"; - interrupts-extended = <&L9 2>; + interrupts-extended = <&L13 2>; linux,code = "none"; }; switch@3 { compatible = "sifive,gpio-switches"; label = "SW3"; - interrupts-extended = <&L10 3>; + interrupts-extended = <&L14 3>; linux,code = "none"; }; - L7: teststatus@4000 { + L12: teststatus@4000 { compatible = "sifive,test0"; reg = <0x4000 0x1000>; reg-names = "control"; diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h index 4ee37f3..89f5d76 100644 --- a/bsp/coreip-s51-arty/metal.h +++ b/bsp/coreip-s51-arty/metal.h @@ -235,10 +235,10 @@ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_exter /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, - .interrupt_lines[0] = 1, - .interrupt_lines[1] = 2, - .interrupt_lines[2] = 3, - .interrupt_lines[3] = 4, + .interrupt_lines[0] = 23, + .interrupt_lines[1] = 24, + .interrupt_lines[2] = 25, + .interrupt_lines[3] = 26, }; /* From gpio@20002000 */ @@ -249,22 +249,22 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = { /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, - .interrupt_lines[0] = 7, - .interrupt_lines[1] = 8, - .interrupt_lines[2] = 9, - .interrupt_lines[3] = 10, - .interrupt_lines[4] = 11, - .interrupt_lines[5] = 12, - .interrupt_lines[6] = 13, - .interrupt_lines[7] = 14, - .interrupt_lines[8] = 15, - .interrupt_lines[9] = 16, - .interrupt_lines[10] = 17, - .interrupt_lines[11] = 18, - .interrupt_lines[12] = 19, - .interrupt_lines[13] = 20, - .interrupt_lines[14] = 21, - .interrupt_lines[15] = 22, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, }; /* From button@0 */ @@ -427,7 +427,7 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_UART_INTERRUPTS, - .interrupt_line = 5UL, + .interrupt_line = 17UL, }; diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 1627f4b..3f994a3 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany diff --git a/bsp/coreip-s51/settings.mk b/bsp/coreip-s51/settings.mk index 553417e..a3cd0bb 100644 --- a/bsp/coreip-s51/settings.mk +++ b/bsp/coreip-s51/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 COREIP_MEM_WIDTH=64 +RISCV_CMODEL=medany diff --git a/bsp/coreip-s54-arty/README.md b/bsp/coreip-s54-arty/README.md new file mode 100644 index 0000000..762c776 --- /dev/null +++ b/bsp/coreip-s54-arty/README.md @@ -0,0 +1,16 @@ +The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities. + +The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-s54-arty/design.dts b/bsp/coreip-s54-arty/design.dts new file mode 100644 index 0000000..7738c2a --- /dev/null +++ b/bsp/coreip-s54-arty/design.dts @@ -0,0 +1,211 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FS510G-dev", "fs510-dev", "sifive-dev"; + model = "SiFive,FS510G"; + chosen { + stdout-path = "/soc/serial@20000000:115200"; + metal,entry = <&L10 0x400000>; + }; + L18: aliases { + serial0 = &L9; + }; + L17: cpus { + #address-cells = <1>; + #size-cells = <0>; + L7: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L10>; + reg = <0x0>; + riscv,isa = "rv64imafdc"; + sifive,dtim = <&L6>; + sifive,itim = <&L5>; + status = "okay"; + timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; + L4: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus"; + ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + L2: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L4 3 &L4 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L3: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L4 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L6: dtim@80000000 { + compatible = "sifive,dtim0"; + reg = <0x80000000 0x10000>; + reg-names = "mem"; + }; + L0: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L13: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; + interrupt-parent = <&L1>; + interrupts = <23 24 25 26>; + }; + L8: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0", "sifive,gpio1"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; + reg = <0x20002000 0x1000>; + reg-names = "control"; + }; + L1: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L4 11>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <26>; + }; + L5: itim@8000000 { + compatible = "sifive,itim0"; + reg = <0x8000000 0x4000>; + reg-names = "mem"; + }; + L14: local-external-interrupts-0 { + compatible = "sifive,local-external-interrupts0"; + interrupt-parent = <&L4>; + interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; + L11: pwm@20005000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L1>; + interrupts = <19 20 21 22>; + reg = <0x20005000 0x1000>; + reg-names = "control"; + }; + L9: serial@20000000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L1>; + interrupts = <17>; + reg = <0x20000000 0x1000>; + reg-names = "control"; + clocks = <&hfclk>; + }; + L10: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sifive,spi0"; + interrupt-parent = <&L1>; + interrupts = <18>; + reg = <0x20004000 0x1000 0x40000000 0x20000000>; + reg-names = "control", "mem"; + }; + led@0red { + compatible = "sifive,gpio-leds"; + label = "LD0red"; + gpios = <&L8 0>; + linux,default-trigger = "none"; + }; + led@0green { + compatible = "sifive,gpio-leds"; + label = "LD0green"; + gpios = <&L8 1>; + linux,default-trigger = "none"; + }; + led@0blue { + compatible = "sifive,gpio-leds"; + label = "LD0blue"; + gpios = <&L8 2>; + linux,default-trigger = "none"; + }; + button@0 { + compatible = "sifive,gpio-buttons"; + label = "BTN0"; + gpios = <&L8 4>; + interrupts-extended = <&L14 4>; + linux,code = "none"; + }; + button@1 { + compatible = "sifive,gpio-buttons"; + label = "BTN1"; + gpios = <&L8 5>; + interrupts-extended = <&L14 5>; + linux,code = "none"; + }; + button@2 { + compatible = "sifive,gpio-buttons"; + label = "BTN2"; + gpios = <&L8 6>; + interrupts-extended = <&L14 6>; + linux,code = "none"; + }; + button@3 { + compatible = "sifive,gpio-buttons"; + label = "BTN3"; + gpios = <&L8 7>; + interrupts-extended = <&L14 7>; + linux,code = "none"; + }; + switch@0 { + compatible = "sifive,gpio-switches"; + label = "SW0"; + interrupts-extended = <&L13 0>; + linux,code = "none"; + }; + switch@1 { + compatible = "sifive,gpio-switches"; + label = "SW1"; + interrupts-extended = <&L13 1>; + linux,code = "none"; + }; + switch@2 { + compatible = "sifive,gpio-switches"; + label = "SW2"; + interrupts-extended = <&L13 2>; + linux,code = "none"; + }; + switch@3 { + compatible = "sifive,gpio-switches"; + label = "SW3"; + interrupts-extended = <&L14 3>; + linux,code = "none"; + }; + L12: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h new file mode 100644 index 0000000..7381117 --- /dev/null +++ b/bsp/coreip-s54-arty/metal.h @@ -0,0 +1,520 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_S54_ARTY__METAL_H +#define COREIP_S54_ARTY__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 2 + +#define METAL_MAX_CLINT_INTERRUPTS 2 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 + +#define METAL_MAX_PLIC_INTERRUPTS 1 + +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define __METAL_LOCAL_EXTERNAL_INTERRUPTS_0_INTERRUPTS 16 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 16 + +#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 4 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 4 + +#define __METAL_GPIO_20002000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_20000000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,local-external-interrupts0.h> +#include <metal/drivers/sifive,global-external-interrupts0.h> +#include <metal/drivers/sifive,gpio0.h> +#include <metal/drivers/sifive,gpio-buttons.h> +#include <metal/drivers/sifive,gpio-leds.h> +#include <metal/drivers/sifive,gpio-switches.h> +#include <metal/drivers/sifive,spi0.h> +#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive,uart0.h> + +/* From clock@0 */ +asm (".weak __metal_dt_clock_0"); +struct __metal_driver_fixed_clock __metal_dt_clock_0; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __metal_dt_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From local_external_interrupts_0 */ +asm (".weak __metal_dt_local_external_interrupts_0"); +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; + +/* From global_external_interrupts */ +asm (".weak __metal_dt_global_external_interrupts"); +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; + +/* From gpio@20002000 */ +asm (".weak __metal_dt_gpio_20002000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000; + +/* From button@0 */ +asm (".weak __metal_dt_button_0"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_0; + +/* From button@1 */ +asm (".weak __metal_dt_button_1"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_1; + +/* From button@2 */ +asm (".weak __metal_dt_button_2"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_2; + +/* From button@3 */ +asm (".weak __metal_dt_button_3"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_3; + +/* From led@0red */ +asm (".weak __metal_dt_led_0red"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red; + +/* From led@0green */ +asm (".weak __metal_dt_led_0green"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green; + +/* From led@0blue */ +asm (".weak __metal_dt_led_0blue"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue; + +/* From switch@0 */ +asm (".weak __metal_dt_switch_0"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0; + +/* From switch@1 */ +asm (".weak __metal_dt_switch_1"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1; + +/* From switch@2 */ +asm (".weak __metal_dt_switch_2"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2; + +/* From switch@3 */ +asm (".weak __metal_dt_switch_3"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3; + +/* From spi@20004000 */ +asm (".weak __metal_dt_spi_20004000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From serial@20000000 */ +asm (".weak __metal_dt_serial_20000000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000; + + +/* From clock@0 */ +struct __metal_driver_fixed_clock __metal_dt_clock_0 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 32500000UL, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_lines[1] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_line = 11UL, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 26UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From local_external_interrupts_0 */ +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { + .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 16, + .interrupt_lines[1] = 17, + .interrupt_lines[2] = 18, + .interrupt_lines[3] = 19, + .interrupt_lines[4] = 20, + .interrupt_lines[5] = 21, + .interrupt_lines[6] = 22, + .interrupt_lines[7] = 23, + .interrupt_lines[8] = 24, + .interrupt_lines[9] = 25, + .interrupt_lines[10] = 26, + .interrupt_lines[11] = 27, + .interrupt_lines[12] = 28, + .interrupt_lines[13] = 29, + .interrupt_lines[14] = 30, + .interrupt_lines[15] = 31, +}; + +/* From global_external_interrupts */ +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { + .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, + .init_done = 0, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 23, + .interrupt_lines[1] = 24, + .interrupt_lines[2] = 25, + .interrupt_lines[3] = 26, +}; + +/* From gpio@20002000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .base = 536879104UL, + .size = 4096UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, +}; + +/* From button@0 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 4UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 4UL, + .label = "BTN0", +}; + +/* From button@1 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 5UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 5UL, + .label = "BTN1", +}; + +/* From button@2 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 6UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 6UL, + .label = "BTN2", +}; + +/* From button@3 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 7UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 7UL, + .label = "BTN3", +}; + +/* From led@0red */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 0UL, + .label = "LD0red", +}; + +/* From led@0green */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 1UL, + .label = "LD0green", +}; + +/* From led@0blue */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 2UL, + .label = "LD0blue", +}; + +/* From switch@0 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 0UL, + .label = "SW0", +}; + +/* From switch@1 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 1UL, + .label = "SW1", +}; + +/* From switch@2 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From global_external_interrupts */ + .interrupt_parent = &__metal_dt_global_external_interrupts.irc, + .interrupt_line = 2UL, + .label = "SW2", +}; + +/* From switch@3 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 3UL, + .label = "SW3", +}; + +/* From spi@20004000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 536887296UL, + .control_size = 4096UL, + .clock = NULL, + .pinmux = NULL, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From serial@20000000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 536870912UL, + .control_size = 4096UL, +/* From clock@0 */ + .clock = &__metal_dt_clock_0.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 17UL, +}; + + +/* From serial@20000000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_SERIAL_20000000_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +/* From cpu@0 */ +#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller */ +#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From local_external_interrupts_0 */ +#define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_LOCAL_EXTERNAL_INTERRUPTS_0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +/* From global_external_interrupts */ +#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_MAX_BUTTONS 4 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + &__metal_dt_button_0, + &__metal_dt_button_1, + &__metal_dt_button_2, + &__metal_dt_button_3}; + +#define __METAL_DT_MAX_LEDS 3 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + &__metal_dt_led_0red, + &__metal_dt_led_0green, + &__metal_dt_led_0blue}; + +#define __METAL_DT_MAX_SWITCHES 4 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + &__metal_dt_switch_0, + &__metal_dt_switch_1, + &__metal_dt_switch_2, + &__metal_dt_switch_3}; + +#define __METAL_DT_MAX_SPIS 1 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_20004000}; + +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_S54_ARTY__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-s54-arty/metal.lds b/bsp/coreip-s54-arty/metal.lds new file mode 100644 index 0000000..28a7849 --- /dev/null +++ b/bsp/coreip-s54-arty/metal.lds @@ -0,0 +1,226 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-s54-arty/openocd.cfg b/bsp/coreip-s54-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-s54-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk new file mode 100644 index 0000000..ab3b474 --- /dev/null +++ b/bsp/coreip-s54-arty/settings.mk @@ -0,0 +1,3 @@ +RISCV_ARCH=rv64imac +RISCV_ABI=lp64 +iRISCV_CMODEL=medany diff --git a/bsp/coreip-s54/settings.mk b/bsp/coreip-s54/settings.mk index 553417e..fabb838 100644 --- a/bsp/coreip-s54/settings.mk +++ b/bsp/coreip-s54/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODE=medany COREIP_MEM_WIDTH=64 diff --git a/bsp/coreip-s76/settings.mk b/bsp/coreip-s76/settings.mk index 553417e..a7d8dfa 100644 --- a/bsp/coreip-s76/settings.mk +++ b/bsp/coreip-s76/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index eacecc3..b7a7782 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -2,3 +2,4 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODE=medlow diff --git a/bsp/sifive-hifive1-revb/README.md b/bsp/sifive-hifive1-revb/README.md new file mode 100644 index 0000000..0cc2af3 --- /dev/null +++ b/bsp/sifive-hifive1-revb/README.md @@ -0,0 +1,13 @@ +HiFive1 Rev B is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts new file mode 100644 index 0000000..5f1797d --- /dev/null +++ b/bsp/sifive-hifive1-revb/design.dts @@ -0,0 +1,196 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sifive,hifive1-revb"; + model = "sifive,hifive1-revb"; + + chosen { + stdout-path = "/soc/serial@10013000:115200"; + metal,entry = <&spi0 0x100000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sifive,fe310-g000"; + L6: cpu@0 { + clocks = <&hfclk>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&spi0>; + reg = <0>; + riscv,isa = "rv32imac"; + sifive,dtim = <&dtim>; + status = "okay"; + timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; + hlic: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + compatible = "sifive,hifive1"; + ranges; + + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + + hfxoscin: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + }; + hfxoscout: clock@1 { + compatible = "sifive,fe310-g000,hfxosc"; + clocks = <&hfxoscin>; + reg = <&prci 0x4>; + reg-names = "config"; + }; + hfroscin: clock@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <72000000>; + }; + hfroscout: clock@3 { + compatible = "sifive,fe310-g000,hfrosc"; + clocks = <&hfroscin>; + reg = <&prci 0x0>; + reg-names = "config"; + }; + hfclk: clock@4 { + compatible = "sifive,fe310-g000,pll"; + clocks = <&hfxoscout &hfroscout>; + clock-names = "pllref", "pllsel0"; + reg = <&prci 0x8 &prci 0xc>; + reg-names = "config", "divider"; + clock-frequency = <16000000>; + }; + + lfroscin: clock@5 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000000>; + }; + lfclk: clock@6 { + compatible = "sifive,fe310-g000,lfrosc"; + clocks = <&lfroscin>; + reg = <&aon 0x70>; + reg-names = "config"; + }; + + aon: aon@10000000 { + compatible = "sifive,aon0"; + reg = <0x10000000 0x8000>; + reg-names = "mem"; + }; + + prci: prci@10008000 { + compatible = "sifive,fe310-g000,prci"; + reg = <0x10008000 0x8000>; + reg-names = "mem"; + }; + + clint: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&hlic 3 &hlic 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + local-external-interrupts-0 { + compatible = "sifive,local-external-interrupts0"; + interrupt-parent = <&hlic>; + interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&hlic 11>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <26>; + }; + global-external-interrupts { + compatile = "sifive,global-external-interrupts0"; + interrupt-parent = <&plic>; + interrupts = <1 2 3 4>; + }; + + debug-controller@0 { + compatible = "sifive,debug-011", "riscv,debug-011"; + interrupts-extended = <&hlic 65535>; + reg = <0x0 0x100>; + reg-names = "control"; + }; + + maskrom@1000 { + reg = <0x1000 0x2000>; + reg-names = "mem"; + }; + otp@20000 { + reg = <0x20000 0x2000 0x10010000 0x1000>; + reg-names = "mem", "control"; + }; + + dtim: dtim@80000000 { + compatible = "sifive,dtim0"; + reg = <0x80000000 0x4000>; + reg-names = "mem"; + }; + + pwm@10015000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26>; + reg = <0x10015000 0x1000>; + reg-names = "control"; + }; + gpio0: gpio@10012000 { + compatible = "sifive,gpio0"; + interrupt-parent = <&plic>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x10012000 0x1000>; + reg-names = "control"; + }; + uart0: serial@10013000 { + compatible = "sifive,uart0"; + interrupt-parent = <&plic>; + interrupts = <5>; + reg = <0x10013000 0x1000>; + reg-names = "control"; + clocks = <&hfclk>; + pinmux = <&gpio0 0x30000 0x30000>; + }; + spi0: spi@10014000 { + compatible = "sifive,spi0"; + interrupt-parent = <&plic>; + interrupts = <6>; + reg = <0x10014000 0x1000 0x20000000 0x20000000>; + reg-names = "control", "mem"; + clocks = <&hfclk>; + pinmux = <&gpio0 0x0003C 0x0003C>; + }; + i2c0: i2c@10016000 { + compatible = "sifive,i2c0"; + interrupt-parent = <&plic>; + interrupts = <52>; + reg = <0x10016000 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h new file mode 100644 index 0000000..4d74b17 --- /dev/null +++ b/bsp/sifive-hifive1-revb/metal.h @@ -0,0 +1,388 @@ +#ifndef ASSEMBLY + +#ifndef SIFIVE_HIFIVE1_REVB__METAL_H +#define SIFIVE_HIFIVE1_REVB__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 2 + +#define METAL_MAX_CLINT_INTERRUPTS 2 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 + +#define METAL_MAX_PLIC_INTERRUPTS 1 + +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define __METAL_LOCAL_EXTERNAL_INTERRUPTS_0_INTERRUPTS 16 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 16 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 0 + +#define __METAL_GPIO_10012000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_10013000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,local-external-interrupts0.h> +#include <metal/drivers/sifive,gpio0.h> +#include <metal/drivers/sifive,spi0.h> +#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive,fe310-g000,hfrosc.h> +#include <metal/drivers/sifive,fe310-g000,hfxosc.h> +#include <metal/drivers/sifive,fe310-g000,pll.h> +#include <metal/drivers/sifive,fe310-g000,prci.h> + +/* From clock@0 */ +asm (".weak __metal_dt_clock_0"); +struct __metal_driver_fixed_clock __metal_dt_clock_0; + +/* From clock@2 */ +asm (".weak __metal_dt_clock_2"); +struct __metal_driver_fixed_clock __metal_dt_clock_2; + +/* From clock@5 */ +asm (".weak __metal_dt_clock_5"); +struct __metal_driver_fixed_clock __metal_dt_clock_5; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __metal_dt_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From local_external_interrupts_0 */ +asm (".weak __metal_dt_local_external_interrupts_0"); +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; + +/* From gpio@10012000 */ +asm (".weak __metal_dt_gpio_10012000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000; + +/* From spi@10014000 */ +asm (".weak __metal_dt_spi_10014000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000; + +/* From serial@10013000 */ +asm (".weak __metal_dt_serial_10013000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000; + +/* From clock@3 */ +asm (".weak __metal_dt_clock_3"); +struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3; + +/* From clock@1 */ +asm (".weak __metal_dt_clock_1"); +struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1; + +/* From clock@4 */ +asm (".weak __metal_dt_clock_4"); +struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4; + +/* From prci@10008000 */ +asm (".weak __metal_dt_prci_10008000"); +struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000; + + +/* From clock@0 */ +struct __metal_driver_fixed_clock __metal_dt_clock_0 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 16000000UL, +}; + +/* From clock@2 */ +struct __metal_driver_fixed_clock __metal_dt_clock_2 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 72000000UL, +}; + +/* From clock@5 */ +struct __metal_driver_fixed_clock __metal_dt_clock_5 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 32000000UL, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_lines[1] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_line = 11UL, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 26UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From local_external_interrupts_0 */ +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { + .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, + .init_done = 0, +/* From interrupt_controller */ + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 16, + .interrupt_lines[1] = 17, + .interrupt_lines[2] = 18, + .interrupt_lines[3] = 19, + .interrupt_lines[4] = 20, + .interrupt_lines[5] = 21, + .interrupt_lines[6] = 22, + .interrupt_lines[7] = 23, + .interrupt_lines[8] = 24, + .interrupt_lines[9] = 25, + .interrupt_lines[10] = 26, + .interrupt_lines[11] = 27, + .interrupt_lines[12] = 28, + .interrupt_lines[13] = 29, + .interrupt_lines[14] = 30, + .interrupt_lines[15] = 31, +}; + +/* From gpio@10012000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10012000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .base = 268509184UL, + .size = 4096UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 7, + .interrupt_lines[1] = 8, + .interrupt_lines[2] = 9, + .interrupt_lines[3] = 10, + .interrupt_lines[4] = 11, + .interrupt_lines[5] = 12, + .interrupt_lines[6] = 13, + .interrupt_lines[7] = 14, + .interrupt_lines[8] = 15, + .interrupt_lines[9] = 16, + .interrupt_lines[10] = 17, + .interrupt_lines[11] = 18, + .interrupt_lines[12] = 19, + .interrupt_lines[13] = 20, + .interrupt_lines[14] = 21, + .interrupt_lines[15] = 22, +}; + +/* From spi@10014000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268517376UL, + .control_size = 4096UL, +/* From clock@4 */ + .clock = &__metal_dt_clock_4.clock, +/* From gpio@10012000 */ + .pinmux = &__metal_dt_gpio_10012000, + .pinmux_output_selector = 60UL, + .pinmux_source_selector = 60UL, +}; + +/* From serial@10013000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 268513280UL, + .control_size = 4096UL, +/* From clock@4 */ + .clock = &__metal_dt_clock_4.clock, +/* From gpio@10012000 */ + .pinmux = &__metal_dt_gpio_10012000, + .pinmux_output_selector = 196608UL, + .pinmux_source_selector = 196608UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 5UL, +}; + +/* From clock@3 */ +struct __metal_driver_sifive_fe310_g000_hfrosc __metal_dt_clock_3 = { + .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc, + .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfrosc.clock, +/* From clock@2 */ + .ref = &__metal_dt_clock_2.clock, +/* From prci@10008000 */ + .config_base = &__metal_dt_prci_10008000, + .config_offset = 0UL, +}; + +/* From clock@1 */ +struct __metal_driver_sifive_fe310_g000_hfxosc __metal_dt_clock_1 = { + .vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc, + .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_hfxosc.clock, +/* From clock@0 */ + .ref = &__metal_dt_clock_0.clock, +/* From prci@10008000 */ + .config_base = &__metal_dt_prci_10008000, + .config_offset = 4UL, +}; + +/* From clock@4 */ +struct __metal_driver_sifive_fe310_g000_pll __metal_dt_clock_4 = { + .vtable = &__metal_driver_vtable_sifive_fe310_g000_pll, + .clock.vtable = &__metal_driver_vtable_sifive_fe310_g000_pll.clock, +/* From clock@3 */ + .pllsel0 = &__metal_dt_clock_3.clock, +/* From clock@1 */ + .pllref = &__metal_dt_clock_1.clock, +/* From prci@10008000 */ + .divider_base = &__metal_dt_prci_10008000, + .divider_offset = 12UL, +/* From prci@10008000 */ + .config_base = &__metal_dt_prci_10008000, + .config_offset = 8UL, + .init_rate = 16000000UL, +}; + +/* From prci@10008000 */ +struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = { + .vtable = &__metal_driver_vtable_sifive_fe310_g000_prci, + .base = 268468224UL, + .size = 32768UL, +}; + + +/* From serial@10013000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10013000.uart) + +#define __METAL_DT_SERIAL_10013000_HANDLE (&__metal_dt_serial_10013000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +/* From cpu@0 */ +#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller */ +#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From local_external_interrupts_0 */ +#define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_LOCAL_EXTERNAL_INTERRUPTS_0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 1 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_10014000}; + +/* From clock@4 */ +#define __METAL_DT_SIFIVE_FE310_G000_PLL_HANDLE (&__metal_dt_clock_4) + +#define __METAL_DT_CLOCK_4_HANDLE (&__metal_dt_clock_4) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* SIFIVE_HIFIVE1_REVB__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/sifive-hifive1-revb/metal.lds b/bsp/sifive-hifive1-revb/metal.lds new file mode 100644 index 0000000..fdd23c7 --- /dev/null +++ b/bsp/sifive-hifive1-revb/metal.lds @@ -0,0 +1,225 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.itim .itim.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >ram AT>flash :ram_init + + + .itim : + { + } >flash AT>flash :flash + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk new file mode 100644 index 0000000..d84238b --- /dev/null +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -0,0 +1,4 @@ +RISCV_ARCH = rv32imac +RISCV_ABI = ilp32 +RISCV_CMODEL = medlow +COREIP_MEM_WIDTH = 32 diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 6311207..d0d0c7a 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -4,7 +4,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index b9424bc..fd73559 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 +RISCV_CMODEL = medlow diff --git a/bsp/update-targets.sh b/bsp/update-targets.sh index 8f094e5..3d7296f 100755 --- a/bsp/update-targets.sh +++ b/bsp/update-targets.sh @@ -29,7 +29,7 @@ done if [[ "$CUSTOM_PATH" == "" && "$CUSTOM_NAME" == "" && "$DTSFILE" == "" ]] then TARGET_LIST="$(ls -d coreip*) " - TARGET_LIST+="sifive-hifive1 freedom-e310-arty " + TARGET_LIST+="sifive-hifive1 sifive-hifive1-revb freedom-e310-arty " else if [[ ! -f "$DTSFILE" && "$DTSFILE" != "*.dts" ]] then |