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2019-03-29Merge pull request #224 from sifive/update-metalNathaniel Graff
Update Metal to v201903
2019-03-29Update Metal to v201903Nathaniel Graff
- Enable RX on the sifive,uart0 driver - Enable FP support in crt0.S - Mark the FE310 PLL config table const Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-29Merge pull request #223 from sifive/codeownersNathaniel Graff
Add nategraff-sifive and bsousi5 as codeowners
2019-03-28Add nategraff-sifive and bsousi5 as codeownersNathaniel Graff
This will cause PRs to automatically request our review Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Merge pull request #220 from sifive/update-docsNathaniel Graff
Update docs for v201903-rc2
2019-03-26Update docs for v201903-rc2Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Set version v201903-rc2Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Fix typo in index.rstNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Merge pull request #218 from sifive/pub-dhrystoneBunnaroath Sou
Making dhrystone public
2019-03-26Update sphinx doc to include dhrystoneBunnaroath Sou
2019-03-26Update readme to include dhrystoneBunnaroath Sou
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #219 from sifive/rename-welcomeNathaniel Graff
Rename example-coreip-welcome to sifive-welcome
2019-03-26Merge pull request #217 from sifive/update-readmeNathaniel Graff
Update the README for targets and commands
2019-03-26Update docs for sifive-welcome renameNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Rename example-coreip-welcome to sifive-welcomeNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
Added design.reglist files to all bsp's based on screenlog output
2019-03-26Update the README for targets and commandsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Merge pull request #216 from sifive/update-makefilesNathaniel Graff
Update all software examples to use wildcards in makefile
2019-03-26Update all software examples to use wildcards in makefileNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Merge pull request #215 from sifive/asflagsNathaniel Graff
Support raw assembly
2019-03-25Set ASFLAGS to workPalmer Dabbelt
This allows users to specify raw assembly files in their build scripts. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-25Merge pull request #214 from sifive/rc1-breakageBunnaroath Sou
Update header to include PLIC, CLIC SUBINTERRUPTS
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-25Merge pull request #213 from sifive/fixup-dtsNathaniel Graff
Add a script which adds missing information to design.dts
2019-03-25Add option to not run fixup-dts to update-targets.shNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-25Run scripts/fixup-dts from update-targets.shNathaniel Graff
2019-03-25Add DTS fixup scriptNathaniel Graff
The script is used as a holdover to add missing elements to design.dts until the IP deliveries catch up with the set of information we need in Freedom E SDK. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-22Initial internal tag 0.0.1 for FS 19.03 RCBunnaroath Sou
2019-03-22Merge pull request #212 from sifive/floating-ptBunnaroath Sou
Pickup floating point support from freedom-metal
2019-03-21Pick metal PLIC fixesBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-19Merge pull request #210 from sifive/extra-output-filesCarsten Gosvig
Added .map + .lst + .rtl extra output files
2019-03-19Merge pull request #209 from sifive/arty-19.2Bunnaroath Sou
Make rtl target to use ram from dtim, flash from testram
2019-03-19Remove accidental added filesBunnaroath Sou
2019-03-19Missed one search and replacecgsfv
2019-03-19Reverted to naming verilog hex files .hexcgsfv
2019-03-19Added .map + .lst + .rtl extra output filescgsfv
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Merge pull request #202 from sifive/arty-19.2Bunnaroath Sou
Add ramrodata, scratchpad linker files, and correct timebase value
2019-03-18Merge pull request #206 from sifive/doc-buildNathaniel Graff
Update the Documentation Makefile
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-18Add link target options to tools and envBunnaroath Sou
2019-03-15Merge pull request #207 from sifive/tagsNathaniel Graff
Proposal: TARGET_TAGS is used to configure the build and to filter list-targets
2019-03-15Merge pull request #208 from sifive/add-readmesNathaniel Graff
Add missing READMEs to software examples
2019-03-15Add missing READMEs to software examplesNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-15Mark list-* as PHONYNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 22:08:19 +0000