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AgeCommit message (Expand)Author
2019-03-26Update sphinx doc to include dhrystoneBunnaroath Sou
2019-03-26Update readme to include dhrystoneBunnaroath Sou
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #219 from sifive/rename-welcomeNathaniel Graff
2019-03-26Merge pull request #217 from sifive/update-readmeNathaniel Graff
2019-03-26Update docs for sifive-welcome renameNathaniel Graff
2019-03-26Rename example-coreip-welcome to sifive-welcomeNathaniel Graff
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
2019-03-26Update the README for targets and commandsNathaniel Graff
2019-03-26Merge pull request #216 from sifive/update-makefilesNathaniel Graff
2019-03-26Update all software examples to use wildcards in makefileNathaniel Graff
2019-03-26Merge pull request #215 from sifive/asflagsNathaniel Graff
2019-03-25Set ASFLAGS to workPalmer Dabbelt
2019-03-25Merge pull request #214 from sifive/rc1-breakageBunnaroath Sou
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-25Merge pull request #213 from sifive/fixup-dtsNathaniel Graff
2019-03-25Add option to not run fixup-dts to update-targets.shNathaniel Graff
2019-03-25Run scripts/fixup-dts from update-targets.shNathaniel Graff
2019-03-25Add DTS fixup scriptNathaniel Graff
2019-03-22Initial internal tag 0.0.1 for FS 19.03 RCBunnaroath Sou
2019-03-22Merge pull request #212 from sifive/floating-ptBunnaroath Sou
2019-03-21Pick metal PLIC fixesBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-19Merge pull request #210 from sifive/extra-output-filesCarsten Gosvig
2019-03-19Merge pull request #209 from sifive/arty-19.2Bunnaroath Sou
2019-03-19Remove accidental added filesBunnaroath Sou
2019-03-19Missed one search and replacecgsfv
2019-03-19Reverted to naming verilog hex files .hexcgsfv
2019-03-19Added .map + .lst + .rtl extra output filescgsfv
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Merge pull request #202 from sifive/arty-19.2Bunnaroath Sou
2019-03-18Merge pull request #206 from sifive/doc-buildNathaniel Graff
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-18Add link target options to tools and envBunnaroath Sou
2019-03-15Merge pull request #207 from sifive/tagsNathaniel Graff
2019-03-15Merge pull request #208 from sifive/add-readmesNathaniel Graff
2019-03-15Add missing READMEs to software examplesNathaniel Graff
2019-03-15Mark list-* as PHONYNathaniel Graff
2019-03-15Add the list-target-tags make targetNathaniel Graff
2019-03-14list-targets accepts TARGET_REQUIRE_TAGS as filterNathaniel Graff
2019-03-14BSPs are any directory with settings.mkNathaniel Graff
2019-03-14Remove SEGGER_JLINK_OB from settings.mkNathaniel Graff
2019-03-14Use TARGET_TAGS in MakefileNathaniel Graff
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
2019-03-14Create TARGET_TAGSNathaniel Graff
2019-03-14Document the githubpages Sphinx module in conf.pyNathaniel Graff
2019-03-14Documentation clean target cleans betterNathaniel Graff
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