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2019-08-31Add dirty helper scriptsuseTimerIRQSilvan Jegen
2019-08-31software/first: remove unused delay.S fileSilvan Jegen
2019-08-31first: remove unused assembly fileSilvan Jegen
2019-08-31software/first: add missed filesSilvan Jegen
2019-08-24setup_timer_irq: remove debugging loadsSilvan Jegen
2019-08-24setup_timer_irq: don't shift ISR address to the leftSilvan Jegen
2019-08-24setup_timer_irq: load ISR with correct instructionSilvan Jegen
We also make sure that the alignment of the ISR is correct. Thanks to the internet for this one as well!
2019-08-24setup_timer_irq: check that we handle the correct IRQSilvan Jegen
2019-08-24setup_timer_irq: set correct MIE bitSilvan Jegen
I got it wrong before but thanks to the internet, I found out about it.
2019-08-24first: introduce wait_for_irqSilvan Jegen
2019-08-24delay: load/write high and low valueSilvan Jegen
I don't think this should make a difference in practice.
2019-08-17Call delay in ISRSilvan Jegen
2019-08-10Implement first version of ISRSilvan Jegen
2019-08-01Start implementing irq setup and handlingSilvan Jegen
2019-07-23first: fix tabs vs. spacesSilvan Jegen
2019-07-22Implement first superblink versionSilvan Jegen
2019-06-21Merge pull request #295 from sifive/update-targetsNathaniel Graff
Fix OpenOCD cfg and remove warnings
2019-06-21Fix OpenOCD cfg and remove warningsNathaniel Graff
Fix OpenOCD config generator for hifive boards Remove some warnings for FE310-compatible targets related to clocks and the PRCI. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Merge pull request #293 from sifive/update-targetsNathaniel Graff
Update BSPs
2019-06-21Merge pull request #294 from sifive/update-docsNathaniel Graff
Update docs
2019-06-21Update published docsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Remove under construction noticeNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Update targetsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Change compat on S51 QEMU nodesNathaniel Graff
Compat strings need to match the FE310 ones to get support from the FE310 drivers. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Update docs for contents of SDKNathaniel Graff
Remove mention of the coreip, add QEMU targets Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Merge pull request #292 from sifive/update-docsNathaniel Graff
Update docs for 19.05
2019-06-21Update docs for 19.05Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Merge pull request #290 from sifive/bump-submodulesNathaniel Graff
Bump Metal and DeviceTree Tools submodules to latest master
2019-06-21Merge pull request #291 from sifive/fix-list-targetsNathaniel Graff
Default target is the first BSP
2019-06-21Default target is the first BSPNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Bump Metal and DeviceTree Tools submodules to latest masterNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-21Merge pull request #287 from sifive/remove-coreip-bspsNathaniel Graff
Remove all CoreIP BSPs
2019-06-21Merge pull request #284 from sifive/remove-pmp-fixupNathaniel Graff
Don't add riscv,pmpregions to DTS
2019-06-21Merge pull request #289 from sifive/fix-list-targetsNathaniel Graff
Fix list targets
2019-06-21Allow list-* targets to work without specifying a valid TARGETKevin Mills
2019-06-20Merge pull request #288 from sifive/fix-benchmark-standalone-buildsNathaniel Graff
Fix benchmark standalone builds
2019-06-20make "clean" work too.Kevin Mills
2019-06-20fixup standalone targets to work.Kevin Mills
2019-06-19Merge pull request #286 from sifive/generate-openocd-cfgNathaniel Graff
update-targets.sh generates openocd.cfg
2019-06-19update-targets updates everything in the bsp folderNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-19Delete coreip BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-19update-targets.sh generates openocd.cfgNathaniel Graff
Generates for Arty and HiFive targets which don't have "jlink" in TARGET_TAGS Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-18Merge pull request #285 from sifive/benchmark-debug-flagsNathaniel Graff
Reorder CFLAGS for benchmarks
2019-06-17Reorder CFLAGS for benchmarksNathaniel Graff
Add benchmark flags after loading the flags for the configuration so that the benchmarks can override the configuration's flags. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-14Merge pull request #267 from sifive/test-coreip-assemblyNathaniel Graff
add test-coreip assembly test
2019-06-14add test-coreip assembly testDavid Connelly
2019-06-14Merge pull request #270 from sifive/qemu-integrationNathaniel Graff
Adding QEMU BSP's for E31 and S51 targets
2019-06-14Don't add riscv,pmpregions to DTSNathaniel Graff
19.05-generated hardware no longer needs this, and adding the node to targets which don't support PMPs causes the wrong failure when trying to use the Metal PMP API. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-06-13Merge pull request #283 from sifive/fixup-no-testramNathaniel Graff
Don't add a testram in fixup-dts
2019-06-13Adding ref to matching QEMU repocgsfv
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